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authorPaul Mundt <lethal@linux-sh.org>2012-05-19 11:50:09 +0200
committerPaul Mundt <lethal@linux-sh.org>2012-05-19 11:50:09 +0200
commite24cca19babe33a7d05712df041f5abbeca4f1bf (patch)
tree59eac5df17932f08b2283ecf036dec2698f79d5f /arch/sh/include
parentsh: Tidy up some of the cpu legacy dma header mess. (diff)
downloadlinux-e24cca19babe33a7d05712df041f5abbeca4f1bf.tar.xz
linux-e24cca19babe33a7d05712df041f5abbeca4f1bf.zip
sh: Kill off MAX_DMA_ADDRESS leftovers.
We don't support the ISA DMA API, so this is only ever misused. The dma-sh case inadvertently broke the dreamcast case by testing the wrong variable for the total number of channels, so this fixes that up too. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include')
-rw-r--r--arch/sh/include/asm/dma-sh.h16
-rw-r--r--arch/sh/include/asm/dma.h8
-rw-r--r--arch/sh/include/mach-dreamcast/mach/dma.h2
3 files changed, 8 insertions, 18 deletions
diff --git a/arch/sh/include/asm/dma-sh.h b/arch/sh/include/asm/dma-sh.h
index f3acb8e34c6b..9a4875a89636 100644
--- a/arch/sh/include/asm/dma-sh.h
+++ b/arch/sh/include/asm/dma-sh.h
@@ -32,21 +32,21 @@
#endif
static int dmte_irq_map[] __maybe_unused = {
-#if (MAX_DMA_CHANNELS >= 4)
+#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 4)
DMTE0_IRQ,
DMTE0_IRQ + 1,
DMTE0_IRQ + 2,
DMTE0_IRQ + 3,
#endif
-#if (MAX_DMA_CHANNELS >= 6)
+#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 6)
DMTE4_IRQ,
DMTE4_IRQ + 1,
#endif
-#if (MAX_DMA_CHANNELS >= 8)
+#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 8)
DMTE6_IRQ,
DMTE6_IRQ + 1,
#endif
-#if (MAX_DMA_CHANNELS >= 12)
+#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 12)
DMTE8_IRQ,
DMTE9_IRQ,
DMTE10_IRQ,
@@ -62,21 +62,21 @@ static int dmte_irq_map[] __maybe_unused = {
/* DMA base address */
static u32 dma_base_addr[] __maybe_unused = {
-#if (MAX_DMA_CHANNELS >= 4)
+#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 4)
SH_DMAC_BASE0 + 0x00, /* channel 0 */
SH_DMAC_BASE0 + 0x10,
SH_DMAC_BASE0 + 0x20,
SH_DMAC_BASE0 + 0x30,
#endif
-#if (MAX_DMA_CHANNELS >= 6)
+#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 6)
SH_DMAC_BASE0 + 0x50,
SH_DMAC_BASE0 + 0x60,
#endif
-#if (MAX_DMA_CHANNELS >= 8)
+#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 8)
SH_DMAC_BASE1 + 0x00,
SH_DMAC_BASE1 + 0x10,
#endif
-#if (MAX_DMA_CHANNELS >= 12)
+#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 12)
SH_DMAC_BASE1 + 0x20,
SH_DMAC_BASE1 + 0x30,
SH_DMAC_BASE1 + 0x50,
diff --git a/arch/sh/include/asm/dma.h b/arch/sh/include/asm/dma.h
index e6c2871a00e7..fb6e4f7b00a2 100644
--- a/arch/sh/include/asm/dma.h
+++ b/arch/sh/include/asm/dma.h
@@ -17,14 +17,6 @@
#include <linux/device.h>
#include <asm-generic/dma.h>
-#ifdef CONFIG_NR_DMA_CHANNELS
-# define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS)
-#elif defined(CONFIG_NR_ONCHIP_DMA_CHANNELS)
-# define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS)
-#else
-# define MAX_DMA_CHANNELS 0
-#endif
-
/*
* Read and write modes can mean drastically different things depending on the
* channel configuration. Consult your DMAC documentation and module
diff --git a/arch/sh/include/mach-dreamcast/mach/dma.h b/arch/sh/include/mach-dreamcast/mach/dma.h
index ddd68e788705..1dbfdf701c9d 100644
--- a/arch/sh/include/mach-dreamcast/mach/dma.h
+++ b/arch/sh/include/mach-dreamcast/mach/dma.h
@@ -11,9 +11,7 @@
#define __ASM_SH_DREAMCAST_DMA_H
/* Number of DMA channels */
-#define ONCHIP_NR_DMA_CHANNELS 4
#define G2_NR_DMA_CHANNELS 4
-#define PVR2_NR_DMA_CHANNELS 1
/* Channels for cascading */
#define PVR2_CASCADE_CHAN 2