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| author | Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> | 2008-06-06 10:04:08 +0200 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2008-07-28 11:10:29 +0200 |
| commit | c63847a3621d2bac054f5709783860ecabd0ee7e (patch) | |
| tree | a04e0aca07d0a672a56b1611544f7d2da0b621e4 /arch/sh/kernel/cpu/sh4a/setup-sh7763.c | |
| parent | sh: Add support Renesas Solutions AP-325RXA board (diff) | |
| download | linux-c63847a3621d2bac054f5709783860ecabd0ee7e.tar.xz linux-c63847a3621d2bac054f5709783860ecabd0ee7e.zip | |
sh: Add SCIF2 support for SH7763.
SH7763 has 3 SCIF device. Current code supports SCIF0 and 1.
SCIF0 and 1 are same register constitution, but only SCIF2 is different.
I added support of SCIF2.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/setup-sh7763.c')
| -rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7763.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c index f189a559462b..3b278df8a53b 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c @@ -3,6 +3,7 @@ * * Copyright (C) 2006 Paul Mundt * Copyright (C) 2007 Yoshihiro Shimoda + * Copyright (C) 2008 Nobuhiro Iwamatsu * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -56,6 +57,11 @@ static struct plat_sci_port sci_platform_data[] = { .type = PORT_SCIF, .irqs = { 76, 77, 79, 78 }, }, { + .mapbase = 0xffe10000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 104, 105, 107, 106 }, + }, { .flags = 0, } }; @@ -208,8 +214,8 @@ static struct intc_vect vectors[] __initdata = { INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60), INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0), INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0), - INTC_VECT(SCIF1_ERI, 0xf00), INTC_VECT(SCIF1_RXI, 0xf20), - INTC_VECT(SCIF1_BRI, 0xf40), INTC_VECT(SCIF1_TXI, 0xf60), + INTC_VECT(SCIF2_ERI, 0xf00), INTC_VECT(SCIF2_RXI, 0xf20), + INTC_VECT(SCIF2_BRI, 0xf40), INTC_VECT(SCIF2_TXI, 0xf60), INTC_VECT(GPIO_CH0, 0xf80), INTC_VECT(GPIO_CH1, 0xfa0), INTC_VECT(GPIO_CH2, 0xfc0), INTC_VECT(GPIO_CH3, 0xfe0), }; |