diff options
| author | Paul Mundt <lethal@linux-sh.org> | 2006-12-28 02:31:48 +0100 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2007-02-13 02:54:44 +0100 |
| commit | 26b7a78c55fbc0e23a7dc19e89fd50f200efc002 (patch) | |
| tree | a830e70a57d4e9cbc669bc362db73ba5ace30d4d /arch/sh/kernel | |
| parent | sh: More tidying for large base pages. (diff) | |
| download | linux-26b7a78c55fbc0e23a7dc19e89fd50f200efc002.tar.xz linux-26b7a78c55fbc0e23a7dc19e89fd50f200efc002.zip | |
sh: Lazy dcache writeback optimizations.
This converts the lazy dcache handling to the model described in
Documentation/cachetlb.txt and drops the ptep_get_and_clear() hacks
used for the aliasing dcaches on SH-4 and SH7705 in 32kB mode. As a
bonus, this slightly cuts down on the cache flushing frequency.
With that and the PTEA handling out of the way, the update_mmu_cache()
implementations can be consolidated, and we no longer have to worry
about which configuration the cache is in for the SH7705 case.
And finally, explicitly disable the lazy writeback on SMP (SH-4A).
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel')
| -rw-r--r-- | arch/sh/kernel/cpu/sh4/probe.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c index 9031a22a2ce7..b26e2bc5894d 100644 --- a/arch/sh/kernel/cpu/sh4/probe.c +++ b/arch/sh/kernel/cpu/sh4/probe.c @@ -181,10 +181,6 @@ int __init detect_cpu_and_cache_system(void) cpu_data->dcache.ways = 1; #endif -#ifdef CONFIG_CPU_HAS_PTEA - cpu_data->flags |= CPU_HAS_PTEA; -#endif - /* * On anything that's not a direct-mapped cache, look to the CVR * for I/D-cache specifics. |