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authorMatt Fleming <matt@console-pimps.org>2010-03-21 20:51:52 +0100
committerPaul Mundt <lethal@linux-sh.org>2010-03-23 05:36:21 +0100
commitb5b6c7eea1124de5b110a48ac62650a690ed2419 (patch)
treed87983aa0d009f6cfc5813f67bc4beffbd4fadf2 /arch/sh/mm/pmb.c
parentsh: Flush ITLB too in PTEAEX's flush_tlb_page() (diff)
downloadlinux-b5b6c7eea1124de5b110a48ac62650a690ed2419.tar.xz
linux-b5b6c7eea1124de5b110a48ac62650a690ed2419.zip
sh: Replace unsafe manipulation of MMUCR
Setting the TI in MMUCR causes all the TLB bits in MMUCR to be cleared. Unfortunately, the TLB wired bits are also cleared when setting the TI bit, causing any wired TLB entries to become unwired. Use local_flush_tlb_all() which implements TLB flushing in a safer manner by using the memory-mapped TLB registers. As each CPU has its own PMB the modifications in pmb_init() only affect the local CPU, so only flush the local CPU's TLB. Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/mm/pmb.c')
-rw-r--r--arch/sh/mm/pmb.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/sh/mm/pmb.c b/arch/sh/mm/pmb.c
index a4662e2782c3..0b14dcf05da7 100644
--- a/arch/sh/mm/pmb.c
+++ b/arch/sh/mm/pmb.c
@@ -802,7 +802,7 @@ void __init pmb_init(void)
writel_uncached(0, PMB_IRMCR);
/* Flush out the TLB */
- __raw_writel(__raw_readl(MMUCR) | MMUCR_TI, MMUCR);
+ local_flush_tlb_all();
ctrl_barrier();
}