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| author | Rich Felker <dalias@libc.org> | 2016-02-15 19:36:33 +0100 |
|---|---|---|
| committer | Rich Felker <dalias@libc.org> | 2016-08-05 05:29:40 +0200 |
| commit | a1e262f6f126466f51d6955fb5bd6aaf0aacf68f (patch) | |
| tree | c03511d896afb2d09b445766b9605f358514e7fe /arch/sh | |
| parent | sh: add SMP support for J2 (diff) | |
| download | linux-a1e262f6f126466f51d6955fb5bd6aaf0aacf68f.tar.xz linux-a1e262f6f126466f51d6955fb5bd6aaf0aacf68f.zip | |
sh: do not perform IPI-based cache flush except on boards that need it
Signed-off-by: Rich Felker <dalias@libc.org>
Diffstat (limited to 'arch/sh')
| -rw-r--r-- | arch/sh/mm/cache.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/sh/mm/cache.c b/arch/sh/mm/cache.c index 70cc52f2fab8..36554a9ea99b 100644 --- a/arch/sh/mm/cache.c +++ b/arch/sh/mm/cache.c @@ -42,6 +42,8 @@ static inline void cacheop_on_each_cpu(void (*func) (void *info), void *info, { preempt_disable(); + /* Needing IPI for cross-core flush is SHX3-specific. */ +#ifdef CONFIG_CPU_SHX3 /* * It's possible that this gets called early on when IRQs are * still disabled due to ioremapping by the boot CPU, so don't @@ -49,6 +51,7 @@ static inline void cacheop_on_each_cpu(void (*func) (void *info), void *info, */ if (num_online_cpus() > 1) smp_call_function(func, info, wait); +#endif func(info); |