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| author | Hideo Saito <saito@densan.co.jp> | 2008-02-14 06:45:08 +0100 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2008-02-14 06:45:08 +0100 |
| commit | a602cc05f8fc849023e72e2857bd842f0104f648 (patch) | |
| tree | 347a49a0339b867c73e9d2c6b8644966841e7c6d /arch/sh | |
| parent | sh: fix pci io access for r2d boards (diff) | |
| download | linux-a602cc05f8fc849023e72e2857bd842f0104f648.tar.xz linux-a602cc05f8fc849023e72e2857bd842f0104f648.zip | |
sh: Fix multiple UTLB hit on UP SH-4.
This acts as a reversion of 1c6b2ca5e0939bf8b5d1a11f1646f25189ecd447 in
the case of UP SH-4, where we still have the risk of a multiple hit
between the slow and fast paths. As seen on SH7780.
Signed-off-by: Hideo Saito <saito@densan.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
| -rw-r--r-- | arch/sh/mm/fault_32.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c index 4ef0a1f1a9ab..d1fa27594c6e 100644 --- a/arch/sh/mm/fault_32.c +++ b/arch/sh/mm/fault_32.c @@ -299,6 +299,14 @@ asmlinkage int __kprobes __do_page_fault(struct pt_regs *regs, entry = pte_mkdirty(entry); entry = pte_mkyoung(entry); +#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SMP) + /* + * ITLB is not affected by "ldtlb" instruction. + * So, we need to flush the entry by ourselves. + */ + local_flush_tlb_one(get_asid(), address & PAGE_MASK); +#endif + set_pte(pte, entry); update_mmu_cache(NULL, address, entry); |