diff options
| author | Magnus Damm <damm@igel.co.jp> | 2009-05-28 14:06:17 +0200 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2009-06-01 08:57:12 +0200 |
| commit | 1823f6d5e6b81cca6542ed2e5f30d2556aad0f67 (patch) | |
| tree | 1a51e8681754b643c745f531db213664dbfb5bef /arch/sh | |
| parent | sh: sh7785lcr mode pin configuration (diff) | |
| download | linux-1823f6d5e6b81cca6542ed2e5f30d2556aad0f67.tar.xz linux-1823f6d5e6b81cca6542ed2e5f30d2556aad0f67.zip | |
sh: sh7785 pll configuration from mode pin
This patch modifies the sh7785 clock code to use the MODE4
value to switch between 72x and 36x PLL multiplication.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
| -rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7785.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c index a4a9bcbec664..705b023f8220 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c @@ -16,6 +16,7 @@ #include <linux/cpufreq.h> #include <asm/clock.h> #include <asm/freq.h> +#include <cpu/sh7785.h> static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, 24, 32, 36, 48 }; @@ -80,12 +81,11 @@ static struct clk_ops frqmr_clk_ops = { static unsigned long pll_recalc(struct clk *clk) { - /* - * XXX: PLL1 multiplier is locked for the default clock mode, - * when mode pin detection and configuration support is added, - * select the multiplier dynamically. - */ - return clk->parent->rate * 36; + int multiplier; + + multiplier = test_mode_pin(MODE_PIN_MODE4) ? 36 : 72; + + return clk->parent->rate * multiplier; } static struct clk_ops pll_clk_ops = { |