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| author | David S. Miller <davem@davemloft.net> | 2012-08-17 08:31:59 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2012-08-19 08:26:19 +0200 |
| commit | ce4a925c29208cf48084d9fa174d965a65246a8d (patch) | |
| tree | 9b99aafebe393782e602d6960da416dd36bb89e8 /arch/sparc/kernel/pcr.c | |
| parent | sparc64: Abstract away the NMI PIC counter computation. (diff) | |
| download | linux-ce4a925c29208cf48084d9fa174d965a65246a8d.tar.xz linux-ce4a925c29208cf48084d9fa174d965a65246a8d.zip | |
sparc64: Abstract away the %pcr values used to enable/disable NMI
We assumed PCR_PIC_PRIV can always be used to disable it, but that
won't be true for SPARC-T4.
This allows us also to get rid of some messy defines used in only
one location.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc/kernel/pcr.c')
| -rw-r--r-- | arch/sparc/kernel/pcr.c | 37 |
1 files changed, 17 insertions, 20 deletions
diff --git a/arch/sparc/kernel/pcr.c b/arch/sparc/kernel/pcr.c index 494af3227f3b..e408fc5d0c18 100644 --- a/arch/sparc/kernel/pcr.c +++ b/arch/sparc/kernel/pcr.c @@ -20,14 +20,6 @@ * perf_event support layer. */ -#define PCR_SUN4U_ENABLE (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE) -#define PCR_N2_ENABLE (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE | \ - PCR_N2_TOE_OV1 | \ - (2 << PCR_N2_SL1_SHIFT) | \ - (0xff << PCR_N2_MASK1_SHIFT)) - -u64 pcr_enable; - /* Performance counter interrupts run unmasked at PIL level 15. * Therefore we can't do things like wakeups and other work * that expects IRQ disabling to be adhered to in locking etc. @@ -105,11 +97,13 @@ static u64 direct_picl_value(unsigned int nmi_hz) } static const struct pcr_ops direct_pcr_ops = { - .read_pcr = direct_pcr_read, - .write_pcr = direct_pcr_write, - .read_pic = direct_pic_read, - .write_pic = direct_pic_write, - .nmi_picl_value = direct_picl_value, + .read_pcr = direct_pcr_read, + .write_pcr = direct_pcr_write, + .read_pic = direct_pic_read, + .write_pic = direct_pic_write, + .nmi_picl_value = direct_picl_value, + .pcr_nmi_enable = (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE), + .pcr_nmi_disable = PCR_PIC_PRIV, }; static void n2_pcr_write(unsigned long reg_num, u64 val) @@ -133,11 +127,16 @@ static u64 n2_picl_value(unsigned int nmi_hz) } static const struct pcr_ops n2_pcr_ops = { - .read_pcr = direct_pcr_read, - .write_pcr = n2_pcr_write, - .read_pic = direct_pic_read, - .write_pic = direct_pic_write, - .nmi_picl_value = n2_picl_value, + .read_pcr = direct_pcr_read, + .write_pcr = n2_pcr_write, + .read_pic = direct_pic_read, + .write_pic = direct_pic_write, + .nmi_picl_value = n2_picl_value, + .pcr_nmi_enable = (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE | + PCR_N2_TOE_OV1 | + (2 << PCR_N2_SL1_SHIFT) | + (0xff << PCR_N2_MASK1_SHIFT)), + .pcr_nmi_disable = PCR_PIC_PRIV, }; static unsigned long perf_hsvc_group; @@ -194,13 +193,11 @@ int __init pcr_arch_init(void) switch (tlb_type) { case hypervisor: pcr_ops = &n2_pcr_ops; - pcr_enable = PCR_N2_ENABLE; break; case cheetah: case cheetah_plus: pcr_ops = &direct_pcr_ops; - pcr_enable = PCR_SUN4U_ENABLE; break; case spitfire: |