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authorfrançois romieu <romieu@fr.zoreil.com>2012-04-17 13:11:40 +0200
committerDavid S. Miller <davem@davemloft.net>2012-04-18 04:54:13 +0200
commit0c20494050a848af4479dbaa89e632a8c5903cf3 (patch)
treebd869102a3f5f6b071d097e756b5e0293572f61c /arch/sparc/net
parentnet: filter: Fix some more small issues in sparc JIT. (diff)
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dmfe: enforce consistent timing delay.
The driver does not always use the same timing for what looks like the same operations. - DCR0 Use the same udelay everywhere for reset. Upper bound is 100 us. - DCR9 Use 5us delay for srom clock. 1us delay for phy_write_1bit (writes PHY_DATA_[01]) are not changed as they stay withing a 2,5MHz MDIO clock range. Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Reviewed-by: Grant Grundler <grundler@parisc-linux.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc/net')
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