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author | David S. Miller <davem@davemloft.net> | 2010-01-05 08:16:03 +0100 |
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committer | David S. Miller <davem@davemloft.net> | 2010-01-05 08:16:03 +0100 |
commit | e04ed38d4e0cd32141f723560efcc8252b0241e2 (patch) | |
tree | f4beace901f1aff12d5f5532b3e1aa615bf6503d /arch/sparc | |
parent | sparc64: Fix NMI programming when perf events are active. (diff) | |
download | linux-e04ed38d4e0cd32141f723560efcc8252b0241e2.tar.xz linux-e04ed38d4e0cd32141f723560efcc8252b0241e2.zip |
sparc64: Fix Niagara2 perf event handling.
For chips like Niagara2 that have true overflow indications
in the %pcr (which we don't actually need and don't use)
the interrupt signal persists until the overflow bits are
cleared by an explicit %pcr write.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc')
-rw-r--r-- | arch/sparc/kernel/perf_event.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c index fa5936e1c3b9..198fb4e79ba2 100644 --- a/arch/sparc/kernel/perf_event.c +++ b/arch/sparc/kernel/perf_event.c @@ -986,6 +986,17 @@ static int __kprobes perf_event_nmi_handler(struct notifier_block *self, data.addr = 0; cpuc = &__get_cpu_var(cpu_hw_events); + + /* If the PMU has the TOE IRQ enable bits, we need to do a + * dummy write to the %pcr to clear the overflow bits and thus + * the interrupt. + * + * Do this before we peek at the counters to determine + * overflow so we don't lose any events. + */ + if (sparc_pmu->irq_bit) + pcr_ops->write(cpuc->pcr); + for (idx = 0; idx < MAX_HWEVENTS; idx++) { struct perf_event *event = cpuc->events[idx]; struct hw_perf_event *hwc; |