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authorMark Brown <broonie@opensource.wolfsonmicro.com>2010-08-16 19:42:58 +0200
committerMark Brown <broonie@opensource.wolfsonmicro.com>2010-08-16 19:42:58 +0200
commite4862f2f6f5653dfb67f3ba2b6f0bc74516ed51a (patch)
tree1db5a0540a4eecfad9b7daee476b985e82ddc810 /arch/tile/include/asm/cache.h
parentMerge branch 'for-2.6.36' of git://git.kernel.org/pub/scm/linux/kernel/git/br... (diff)
parentASoC: Remove DSP mode support for WM8776 (diff)
downloadlinux-e4862f2f6f5653dfb67f3ba2b6f0bc74516ed51a.tar.xz
linux-e4862f2f6f5653dfb67f3ba2b6f0bc74516ed51a.zip
Merge branch 'for-2.6.36' into for-2.6.37
Fairly simple conflicts, the most serious ones are the i.MX ones which I suspect now need another rename. Conflicts: arch/arm/mach-mx2/clock_imx27.c arch/arm/mach-mx2/devices.c arch/arm/mach-omap2/board-rx51-peripherals.c arch/arm/mach-omap2/board-zoom2.c sound/soc/fsl/mpc5200_dma.c sound/soc/fsl/mpc5200_dma.h sound/soc/fsl/mpc8610_hpcd.c sound/soc/pxa/spitz.c
Diffstat (limited to 'arch/tile/include/asm/cache.h')
-rw-r--r--arch/tile/include/asm/cache.h51
1 files changed, 51 insertions, 0 deletions
diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h
new file mode 100644
index 000000000000..08a2815b5e4e
--- /dev/null
+++ b/arch/tile/include/asm/cache.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2010 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _ASM_TILE_CACHE_H
+#define _ASM_TILE_CACHE_H
+
+#include <arch/chip.h>
+
+/* bytes per L1 data cache line */
+#define L1_CACHE_SHIFT CHIP_L1D_LOG_LINE_SIZE()
+#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+
+/* bytes per L2 cache line */
+#define L2_CACHE_SHIFT CHIP_L2_LOG_LINE_SIZE()
+#define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT)
+#define L2_CACHE_ALIGN(x) (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES)
+
+/*
+ * TILE-Gx is fully coherent so we don't need to define ARCH_DMA_MINALIGN.
+ */
+#ifndef __tilegx__
+#define ARCH_DMA_MINALIGN L2_CACHE_BYTES
+#endif
+
+/* use the cache line size for the L2, which is where it counts */
+#define SMP_CACHE_BYTES_SHIFT L2_CACHE_SHIFT
+#define SMP_CACHE_BYTES L2_CACHE_BYTES
+#define INTERNODE_CACHE_SHIFT L2_CACHE_SHIFT
+#define INTERNODE_CACHE_BYTES L2_CACHE_BYTES
+
+/* Group together read-mostly things to avoid cache false sharing */
+#define __read_mostly __attribute__((__section__(".data.read_mostly")))
+
+/*
+ * Attribute for data that is kept read/write coherent until the end of
+ * initialization, then bumped to read/only incoherent for performance.
+ */
+#define __write_once __attribute__((__section__(".w1data")))
+
+#endif /* _ASM_TILE_CACHE_H */