diff options
| author | Chris Metcalf <cmetcalf@tilera.com> | 2012-03-29 21:25:59 +0200 |
|---|---|---|
| committer | Chris Metcalf <cmetcalf@tilera.com> | 2012-05-25 18:48:24 +0200 |
| commit | cd6f32aa088f4d328e676c35f51b440f2fe5b98c (patch) | |
| tree | 5668ff37a8690e5f5d919992756edb4466c37de2 /arch/tile/include/asm/syscalls.h | |
| parent | arch/tile: Allow tilegx to build with either 16K or 64K page size (diff) | |
| download | linux-cd6f32aa088f4d328e676c35f51b440f2fe5b98c.tar.xz linux-cd6f32aa088f4d328e676c35f51b440f2fe5b98c.zip | |
arch/tile: support <asm/cachectl.h> header for cacheflush() syscall
We already had a syscall that did some dcache flushing, but it was
not used in practice. Make it MIPS compatible instead so it can
do both the DCACHE and ICACHE actions. We have code that wants to
be able to use the ICACHE flush mode from userspace so this change
enables that.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile/include/asm/syscalls.h')
| -rw-r--r-- | arch/tile/include/asm/syscalls.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/tile/include/asm/syscalls.h b/arch/tile/include/asm/syscalls.h index 3b5507c31eae..06f0464cfed9 100644 --- a/arch/tile/include/asm/syscalls.h +++ b/arch/tile/include/asm/syscalls.h @@ -43,7 +43,8 @@ long sys32_fadvise64(int fd, u32 offset_lo, u32 offset_hi, u32 len, int advice); int sys32_fadvise64_64(int fd, u32 offset_lo, u32 offset_hi, u32 len_lo, u32 len_hi, int advice); -long sys_flush_cache(void); +long sys_cacheflush(unsigned long addr, unsigned long len, + unsigned long flags); #ifndef __tilegx__ /* No mmap() in the 32-bit kernel. */ #define sys_mmap sys_mmap #endif |