diff options
| author | Chris Metcalf <cmetcalf@tilera.com> | 2013-07-23 23:32:04 +0200 |
|---|---|---|
| committer | Chris Metcalf <cmetcalf@tilera.com> | 2013-07-31 17:51:19 +0200 |
| commit | dd78bc11fb2050b6a3990d0421feca4c68ca4335 (patch) | |
| tree | 7147fe5e0b3815443eea608d3dd0950ba53bb47d /arch/tile/include/uapi | |
| parent | tile: various minor cleanups to hardwall subsystem (diff) | |
| download | linux-dd78bc11fb2050b6a3990d0421feca4c68ca4335.tar.xz linux-dd78bc11fb2050b6a3990d0421feca4c68ca4335.zip | |
tile: convert uses of "inv" to "finv"
The "inv" (invalidate) instruction is generally less safe than "finv"
(flush and invalidate), as it will drop dirty data from the cache.
It turns out we have almost no need for "inv" (other than for the
older 32-bit architecture in some limited cases), so convert to
"finv" where possible and delete the extra "inv" infrastructure.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile/include/uapi')
| -rw-r--r-- | arch/tile/include/uapi/asm/cachectl.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/tile/include/uapi/asm/cachectl.h b/arch/tile/include/uapi/asm/cachectl.h index af4c9f9154d1..572ddcad2090 100644 --- a/arch/tile/include/uapi/asm/cachectl.h +++ b/arch/tile/include/uapi/asm/cachectl.h @@ -29,8 +29,8 @@ * to honor the arguments at some point.) * * Flush and invalidation of memory can normally be performed with the - * __insn_flush(), __insn_inv(), and __insn_finv() instructions from - * userspace. The DCACHE option to the system call allows userspace + * __insn_flush() and __insn_finv() instructions from userspace. + * The DCACHE option to the system call allows userspace * to flush the entire L1+L2 data cache from the core. In this case, * the address and length arguments are not used. The DCACHE flush is * restricted to the current core, not all cores in the address space. |