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| author | Chris Metcalf <cmetcalf@tilera.com> | 2013-08-05 20:27:05 +0200 |
|---|---|---|
| committer | Chris Metcalf <cmetcalf@tilera.com> | 2013-08-06 18:56:08 +0200 |
| commit | 5026dafa177133f9b6bf0000dfc98596fa4ad2fd (patch) | |
| tree | de55adb83145e8815f287a0ef89ce01dbdeaaa30 /arch/tile/include | |
| parent | tile PCI DMA: fix bug in non-page-aligned accessors (diff) | |
| download | linux-5026dafa177133f9b6bf0000dfc98596fa4ad2fd.tar.xz linux-5026dafa177133f9b6bf0000dfc98596fa4ad2fd.zip | |
tile PCI RC: support PCIe TRIO 0 MAC 0 on Gx72 system
On Tilera Gx72 systems, the logic for figuring out whether
a given port is root complex is slightly different.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile/include')
| -rw-r--r-- | arch/tile/include/hv/drv_trio_intf.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/tile/include/hv/drv_trio_intf.h b/arch/tile/include/hv/drv_trio_intf.h index ec643a02b4c5..237e04dee66c 100644 --- a/arch/tile/include/hv/drv_trio_intf.h +++ b/arch/tile/include/hv/drv_trio_intf.h @@ -168,6 +168,9 @@ pcie_stream_intr_config_sel_t; struct pcie_trio_ports_property { struct pcie_port_property ports[TILEGX_TRIO_PCIES]; + + /** Set if this TRIO belongs to a Gx72 device. */ + uint8_t is_gx72; }; /* Flags indicating traffic class. */ |