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authorChris Metcalf <cmetcalf@tilera.com>2012-05-09 18:26:30 +0200
committerChris Metcalf <cmetcalf@tilera.com>2012-07-18 22:40:11 +0200
commiteef015c8aa74451f848307fe5f65485070533bbb (patch)
tree7fca680be2246812c14920c0fb44fbe717786dc6 /arch/tile/kernel/setup.c
parenttilegx pci: support I/O to arbitrarily-cached pages (diff)
downloadlinux-eef015c8aa74451f848307fe5f65485070533bbb.tar.xz
linux-eef015c8aa74451f848307fe5f65485070533bbb.zip
arch/tile: enable ZONE_DMA for tilegx
This is required for PCI root complex legacy support and USB OHCI root complex support. With this change tilegx now supports allocating memory whose PA fits in 32 bits. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile/kernel/setup.c')
-rw-r--r--arch/tile/kernel/setup.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c
index 6d179dfcc15e..fdde3b6986e5 100644
--- a/arch/tile/kernel/setup.c
+++ b/arch/tile/kernel/setup.c
@@ -658,6 +658,8 @@ static void __init zone_sizes_init(void)
unsigned long zones_size[MAX_NR_ZONES] = { 0 };
int size = percpu_size();
int num_cpus = smp_height * smp_width;
+ const unsigned long dma_end = (1UL << (32 - PAGE_SHIFT));
+
int i;
for (i = 0; i < num_cpus; ++i)
@@ -729,6 +731,14 @@ static void __init zone_sizes_init(void)
zones_size[ZONE_NORMAL] = end - start;
#endif
+ if (start < dma_end) {
+ zones_size[ZONE_DMA] = min(zones_size[ZONE_NORMAL],
+ dma_end - start);
+ zones_size[ZONE_NORMAL] -= zones_size[ZONE_DMA];
+ } else {
+ zones_size[ZONE_DMA] = 0;
+ }
+
/* Take zone metadata from controller 0 if we're isolnode. */
if (node_isset(i, isolnodes))
NODE_DATA(i)->bdata = &bootmem_node_data[0];
@@ -738,7 +748,7 @@ static void __init zone_sizes_init(void)
PFN_UP(node_percpu[i]));
/* Track the type of memory on each node */
- if (zones_size[ZONE_NORMAL])
+ if (zones_size[ZONE_NORMAL] || zones_size[ZONE_DMA])
node_set_state(i, N_NORMAL_MEMORY);
#ifdef CONFIG_HIGHMEM
if (end != start)