diff options
author | Chris Metcalf <cmetcalf@tilera.com> | 2013-08-05 20:27:05 +0200 |
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committer | Chris Metcalf <cmetcalf@tilera.com> | 2013-08-06 18:56:08 +0200 |
commit | 5026dafa177133f9b6bf0000dfc98596fa4ad2fd (patch) | |
tree | de55adb83145e8815f287a0ef89ce01dbdeaaa30 /arch/tile/kernel | |
parent | tile PCI DMA: fix bug in non-page-aligned accessors (diff) | |
download | linux-5026dafa177133f9b6bf0000dfc98596fa4ad2fd.tar.xz linux-5026dafa177133f9b6bf0000dfc98596fa4ad2fd.zip |
tile PCI RC: support PCIe TRIO 0 MAC 0 on Gx72 system
On Tilera Gx72 systems, the logic for figuring out whether
a given port is root complex is slightly different.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile/kernel')
-rw-r--r-- | arch/tile/kernel/pci_gx.c | 33 |
1 files changed, 30 insertions, 3 deletions
diff --git a/arch/tile/kernel/pci_gx.c b/arch/tile/kernel/pci_gx.c index de5008b72fa3..f2bf200b641b 100644 --- a/arch/tile/kernel/pci_gx.c +++ b/arch/tile/kernel/pci_gx.c @@ -436,9 +436,26 @@ int __init tile_pci_init(void) /* * Now determine which PCIe ports are configured to operate in RC - * mode. To use a port, it must be allowed to be in RC mode by the + * mode. There is a differece in the port configuration capability + * between the Gx36 and Gx72 devices. + * + * The Gx36 has configuration capability for each of the 3 PCIe + * interfaces (disable, auto endpoint, auto RC, etc.). + * On the Gx72, you can only select one of the 3 PCIe interfaces per + * TRIO to train automatically. Further, the allowable training modes + * are reduced to four options (auto endpoint, auto RC, stream x1, + * stream x4). + * + * For Gx36 ports, it must be allowed to be in RC mode by the * Board Information Block, and the hardware strapping pins must be * set to RC mode. + * + * For Gx72 ports, the port will operate in RC mode if either of the + * following is true: + * 1. It is allowed to be in RC mode by the Board Information Block, + * and the BIB doesn't allow the EP mode. + * 2. It is allowed to be in either the RC or the EP mode by the BIB, + * and the hardware strapping pin is set to RC mode. */ for (i = 0; i < TILEGX_NUM_TRIO; i++) { gxio_trio_context_t *context = &trio_contexts[i]; @@ -447,8 +464,18 @@ int __init tile_pci_init(void) continue; for (j = 0; j < TILEGX_TRIO_PCIES; j++) { - if (pcie_ports[i].ports[j].allow_rc && - strapped_for_rc(context, j)) { + int is_rc = 0; + + if (pcie_ports[i].is_gx72 && + pcie_ports[i].ports[j].allow_rc) { + if (!pcie_ports[i].ports[j].allow_ep || + strapped_for_rc(context, j)) + is_rc = 1; + } else if (pcie_ports[i].ports[j].allow_rc && + strapped_for_rc(context, j)) { + is_rc = 1; + } + if (is_rc) { pcie_rc[i][j] = 1; num_rc_controllers++; } |