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| author | Jacob Pan <jacob.jun.pan@intel.com> | 2009-09-02 16:37:17 +0200 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2010-02-24 20:01:21 +0100 |
| commit | bb24c4716185f6e116c440462c65c1f56649183b (patch) | |
| tree | 70af8cb5932207d0b16330f47829bbf084f7b04e /arch/x86/Kconfig | |
| parent | x86, mrst: Add vrtc platform data setup code (diff) | |
| download | linux-bb24c4716185f6e116c440462c65c1f56649183b.tar.xz linux-bb24c4716185f6e116c440462c65c1f56649183b.zip | |
x86, apbt: Moorestown APB system timer driver
Moorestown platform does not have PIT or HPET platform timers. Instead it
has a bank of eight APB timers. The number of available timers to the os
is exposed via SFI mtmr tables. All APB timer interrupts are routed via
ioapic rtes and delivered as MSI.
Currently, we use timer 0 and 1 for per cpu clockevent devices, timer 2
for clocksource.
Signed-off-by: Jacob Pan <jacob.jun.pan@intel.com>
LKML-Reference: <43F901BD926A4E43B106BF17856F0755A318D2D2@orsmsx508.amr.corp.intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/Kconfig')
| -rw-r--r-- | arch/x86/Kconfig | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index eb4092568f9e..0ab2dcef7d84 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -390,6 +390,7 @@ config X86_MRST bool "Moorestown MID platform" depends on X86_32 depends on X86_EXTENDED_PLATFORM + select APB_TIMER ---help--- Moorestown is Intel's Low Power Intel Architecture (LPIA) based Moblin Internet Device(MID) platform. Moorestown consists of two chips: @@ -612,6 +613,16 @@ config HPET_EMULATE_RTC def_bool y depends on HPET_TIMER && (RTC=y || RTC=m || RTC_DRV_CMOS=m || RTC_DRV_CMOS=y) +config APB_TIMER + def_bool y if MRST + prompt "Langwell APB Timer Support" if X86_MRST + help + APB timer is the replacement for 8254, HPET on X86 MID platforms. + The APBT provides a stable time base on SMP + systems, unlike the TSC, but it is more expensive to access, + as it is off-chip. APB timers are always running regardless of CPU + C states, they are used as per CPU clockevent device when possible. + # Mark as embedded because too many people got it wrong. # The code disables itself when not needed. config DMI |