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| author | Kan Liang <kan.liang@linux.intel.com> | 2019-10-08 17:50:08 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2019-10-12 15:13:09 +0200 |
| commit | 23645a76ba816652d6898def2ee69c6a6250c9b1 (patch) | |
| tree | 109d7e94e017ec3a86f471d6379f19d697d7d6b6 /arch/x86/events/msr.c | |
| parent | perf/x86/cstate: Update C-state counters for Ice Lake (diff) | |
| download | linux-23645a76ba816652d6898def2ee69c6a6250c9b1.tar.xz linux-23645a76ba816652d6898def2ee69c6a6250c9b1.zip | |
perf/x86/intel: Add Tiger Lake CPU support
Tiger Lake is the followon to Ice Lake. From the perspective of Intel
core PMU, there is little changes compared with Ice Lake, e.g. small
changes in event list. But it doesn't impact on core PMU functionality.
Share the perf code with Ice Lake. The event list patch will be submitted
later separately.
The patch has been tested on real hardware.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/1570549810-25049-8-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
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