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| author | Len Brown <len.brown@intel.com> | 2017-02-25 17:56:29 +0100 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2017-04-29 06:09:57 +0200 |
| commit | 8d84e906f5db80540510e448226f2718a686eb2a (patch) | |
| tree | dabc653f2893ab4eaef22c372982d48fdc880b82 /arch/x86/include/asm/msr-index.h | |
| parent | x86: msr-index.h: define EPB mid-points (diff) | |
| download | linux-8d84e906f5db80540510e448226f2718a686eb2a.tar.xz linux-8d84e906f5db80540510e448226f2718a686eb2a.zip | |
x86: msr-index.h: define HWP.EPP values
The Hardware Performance State request MSR has a field
to express the "Energy Performance Preference" (HWP.EPP).
Decode that field so the definition may be shared by
by the intel_pstate driver and any utilities that
decode the same register.
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'arch/x86/include/asm/msr-index.h')
| -rw-r--r-- | arch/x86/include/asm/msr-index.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index a92d9bd154f6..50c0c3204a92 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -239,6 +239,10 @@ #define HWP_MAX_PERF(x) ((x & 0xff) << 8) #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) #define HWP_ENERGY_PERF_PREFERENCE(x) ((x & 0xff) << 24) +#define HWP_EPP_PERFORMANCE 0x00 +#define HWP_EPP_BALANCE_PERFORMANCE 0x80 +#define HWP_EPP_BALANCE_POWERSAVE 0xC0 +#define HWP_EPP_POWERSAVE 0xFF #define HWP_ACTIVITY_WINDOW(x) ((x & 0xff3) << 32) #define HWP_PACKAGE_CONTROL(x) ((x & 0x1) << 42) |