diff options
| author | Tony Luck <tony.luck@intel.com> | 2020-10-30 20:04:00 +0100 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2020-11-02 11:15:59 +0100 |
| commit | 68299a42f84288537ee3420c431ac0115ccb90b1 (patch) | |
| tree | a799950b549bf767c61be95bcc8f83275b86bd7e /arch/x86/include/asm/msr-index.h | |
| parent | x86/mce: Remove unneeded break (diff) | |
| download | linux-68299a42f84288537ee3420c431ac0115ccb90b1.tar.xz linux-68299a42f84288537ee3420c431ac0115ccb90b1.zip | |
x86/mce: Enable additional error logging on certain Intel CPUs
The Xeon versions of Sandy Bridge, Ivy Bridge and Haswell support an
optional additional error logging mode which is enabled by an MSR.
Previously, this mode was enabled from the mcelog(8) tool via /dev/cpu,
but userspace should not be poking at MSRs. So move the enabling into
the kernel.
[ bp: Correct the explanation why this is done. ]
Suggested-by: Boris Petkov <bp@alien8.de>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20201030190807.GA13884@agluck-desk2.amr.corp.intel.com
Diffstat (limited to 'arch/x86/include/asm/msr-index.h')
| -rw-r--r-- | arch/x86/include/asm/msr-index.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 972a34d93505..b2dd2648c0e2 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -139,6 +139,7 @@ #define MSR_IA32_MCG_CAP 0x00000179 #define MSR_IA32_MCG_STATUS 0x0000017a #define MSR_IA32_MCG_CTL 0x0000017b +#define MSR_ERROR_CONTROL 0x0000017f #define MSR_IA32_MCG_EXT_CTL 0x000004d0 #define MSR_OFFCORE_RSP_0 0x000001a6 |