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authorIngo Molnar <mingo@kernel.org>2018-10-02 09:50:34 +0200
committerIngo Molnar <mingo@kernel.org>2018-10-02 09:50:34 +0200
commit97e831e13015045c098e1187f9b8b8e9bace9413 (patch)
tree26c4a34a290841a140007bf10a45798b8ea49c44 /arch/x86/include/asm/perf_event.h
parentMerge tag 'perf-core-for-mingo-4.20-20180924' of git://git.kernel.org/pub/scm... (diff)
parentperf/x86/amd/uncore: Set ThreadMask and SliceMask for L3 Cache perf events (diff)
downloadlinux-97e831e13015045c098e1187f9b8b8e9bace9413.tar.xz
linux-97e831e13015045c098e1187f9b8b8e9bace9413.zip
Merge branch 'perf/urgent' into perf/core, to pick up fixes
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/include/asm/perf_event.h')
-rw-r--r--arch/x86/include/asm/perf_event.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 12f54082f4c8..78241b736f2a 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -46,6 +46,14 @@
#define INTEL_ARCH_EVENT_MASK \
(ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)
+#define AMD64_L3_SLICE_SHIFT 48
+#define AMD64_L3_SLICE_MASK \
+ ((0xFULL) << AMD64_L3_SLICE_SHIFT)
+
+#define AMD64_L3_THREAD_SHIFT 56
+#define AMD64_L3_THREAD_MASK \
+ ((0xFFULL) << AMD64_L3_THREAD_SHIFT)
+
#define X86_RAW_EVENT_MASK \
(ARCH_PERFMON_EVENTSEL_EVENT | \
ARCH_PERFMON_EVENTSEL_UMASK | \