diff options
| author | Suresh Siddha <suresh.b.siddha@intel.com> | 2011-11-04 23:42:17 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2011-12-05 18:00:31 +0100 |
| commit | 28a00184be261e3dc152ba0d664a067bbe235b6a (patch) | |
| tree | 9c56ce8c758a244173c9b0016cac43f45609d4ed /arch/x86/include/asm/tsc.h | |
| parent | x86: Fix boot failures on older AMD CPU's (diff) | |
| download | linux-28a00184be261e3dc152ba0d664a067bbe235b6a.tar.xz linux-28a00184be261e3dc152ba0d664a067bbe235b6a.zip | |
x86, tsc: Skip TSC synchronization checks for tsc=reliable
tsc=reliable boot parameter is supposed to skip all the TSC
stablility checks during boot time.
On a 8-socket system where we want to run an experiment with the
"tsc=reliable" boot option, TSC synchronization checks are not
getting skipped and marking the TSC as not stable.
Check for tsc_clocksource_reliable (which is set via
tsc=reliable or for platforms supporting synthetic TSC_RELIABLE
feature bit etc) and when set, skip the TSC synchronization
tests during boot.
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Acked-by: John Stultz <johnstul@us.ibm.com>
Tested-by: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/r/1320446537.15071.14.camel@sbsiddha-desk.sc.intel.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/include/asm/tsc.h')
| -rw-r--r-- | arch/x86/include/asm/tsc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h index 83e2efd181e2..15d99153a96d 100644 --- a/arch/x86/include/asm/tsc.h +++ b/arch/x86/include/asm/tsc.h @@ -51,6 +51,8 @@ extern int unsynchronized_tsc(void); extern int check_tsc_unstable(void); extern unsigned long native_calibrate_tsc(void); +extern int tsc_clocksource_reliable; + /* * Boot-time check whether the TSCs are synchronized across * all CPUs/cores: |