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authorIngo Molnar <mingo@elte.hu>2008-12-17 13:09:20 +0100
committerIngo Molnar <mingo@elte.hu>2008-12-23 12:45:12 +0100
commit862a1a5f346fe7e9181ea51eaae48cf2cd70f746 (patch)
tree6c38478c3197ae842a3fa8ebc1623bc8d3fde6a4 /arch/x86/include
parentperfcounters: add fixed-mode PMC enumeration (diff)
downloadlinux-862a1a5f346fe7e9181ea51eaae48cf2cd70f746.tar.xz
linux-862a1a5f346fe7e9181ea51eaae48cf2cd70f746.zip
x86, perfcounters: refactor code for fixed-function PMCs
Impact: clean up Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/include')
-rw-r--r--arch/x86/include/asm/perf_counter.h14
1 files changed, 13 insertions, 1 deletions
diff --git a/arch/x86/include/asm/perf_counter.h b/arch/x86/include/asm/perf_counter.h
index 945a315e6d62..13745deb16c8 100644
--- a/arch/x86/include/asm/perf_counter.h
+++ b/arch/x86/include/asm/perf_counter.h
@@ -8,6 +8,10 @@
#define X86_PMC_MAX_GENERIC 8
#define X86_PMC_MAX_FIXED 3
+#define X86_PMC_IDX_GENERIC 0
+#define X86_PMC_IDX_FIXED 32
+#define X86_PMC_IDX_MAX 64
+
#define MSR_ARCH_PERFMON_PERFCTR0 0xc1
#define MSR_ARCH_PERFMON_PERFCTR1 0xc2
@@ -54,6 +58,15 @@ union cpuid10_edx {
* Fixed-purpose performance counters:
*/
+/*
+ * All 3 fixed-mode PMCs are configured via this single MSR:
+ */
+#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
+
+/*
+ * The counts are available in three separate MSRs:
+ */
+
/* Instr_Retired.Any: */
#define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
@@ -63,7 +76,6 @@ union cpuid10_edx {
/* CPU_CLK_Unhalted.Ref: */
#define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
-
#ifdef CONFIG_PERF_COUNTERS
extern void init_hw_perf_counters(void);
extern void perf_counters_lapic_init(int nmi);