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authorH. Peter Anvin <hpa@linux.intel.com>2009-01-22 00:04:32 +0100
committerIngo Molnar <mingo@elte.hu>2009-01-22 09:24:02 +0100
commit066941bd4eeb159307a5d7d795100d0887c00442 (patch)
tree2bd4dfc033f72cbe0b3532140f54df1869dd6180 /arch/x86/kernel/cpu/intel.c
parentx86: add MSR_IA32_MISC_ENABLE bits to <asm/msr-index.h> (diff)
downloadlinux-066941bd4eeb159307a5d7d795100d0887c00442.tar.xz
linux-066941bd4eeb159307a5d7d795100d0887c00442.zip
x86: unmask CPUID levels on Intel CPUs
Impact: Fixes crashes with misconfigured BIOSes on XSAVE hardware Avuton Olrich reported early boot crashes with v2.6.28 and bisected it down to dc1e35c6e95e8923cf1d3510438b63c600fee1e2 ("x86, xsave: enable xsave/xrstor on cpus with xsave support"). If the CPUID limit bit in MSR_IA32_MISC_ENABLE is set, clear it to make all CPUID information available. This is required for some features to work, in particular XSAVE. Reported-and-bisected-by: Avuton Olrich <avuton@gmail.com> Tested-by: Avuton Olrich <avuton@gmail.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch/x86/kernel/cpu/intel.c')
-rw-r--r--arch/x86/kernel/cpu/intel.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 8ea6929e974c..43c1dcf0bec7 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -29,6 +29,16 @@
static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
{
+ u64 misc_enable;
+
+ /* Unmask CPUID levels if masked */
+ if (!rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_enable) &&
+ (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID)) {
+ misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
+ wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+ c->cpuid_level = cpuid_eax(0);
+ }
+
if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
(c->x86 == 0x6 && c->x86_model >= 0x0e))
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);