diff options
| author | Andi Kleen <ak@suse.de> | 2008-01-30 13:32:37 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-01-30 13:32:37 +0100 |
| commit | 707fa8ed923b1b6a3d7af0d386b0b3abad28ed19 (patch) | |
| tree | 181c7fe62e4c392486a06380df4da870bfaa40bf /arch/x86/kernel/cpu/intel.c | |
| parent | x86: implement support to synchronize RDTSC through MFENCE on AMD CPUs (diff) | |
| download | linux-707fa8ed923b1b6a3d7af0d386b0b3abad28ed19.tar.xz linux-707fa8ed923b1b6a3d7af0d386b0b3abad28ed19.zip | |
x86: Implement support to synchronize RDTSC with LFENCE on Intel CPUs
According to Intel RDTSC can be always synchronized with LFENCE
on all current CPUs. Implement the necessary CPUID bit for that.
It is unclear yet if that is true for all future CPUs too,
but if there's another way the kernel can be always updated.
Cc: asit.k.mallick@intel.com
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/kernel/cpu/intel.c')
| -rw-r--r-- | arch/x86/kernel/cpu/intel.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index e4b7e73e9024..0a4abdb61ae4 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -203,9 +203,10 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) } #endif + if (cpu_has_xmm) + set_bit(X86_FEATURE_LFENCE_RDTSC, c->x86_capability); if (c->x86 == 15) { set_bit(X86_FEATURE_P4, c->x86_capability); - set_bit(X86_FEATURE_SYNC_RDTSC, c->x86_capability); } if (c->x86 == 6) set_bit(X86_FEATURE_P3, c->x86_capability); |