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| author | Ingo Molnar <mingo@kernel.org> | 2016-07-27 12:35:35 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2016-07-27 12:35:35 +0200 |
| commit | df15929f8f5c69e987c31bf016eca4a38dba46f0 (patch) | |
| tree | cfb5fe5e8ebff4cabd70557a304f355546943cc9 /arch/x86/kernel/cpu/intel.c | |
| parent | x86/microcode/intel: Fix initrd loading with CONFIG_RANDOMIZE_MEMORY=y (diff) | |
| parent | Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/ke... (diff) | |
| download | linux-df15929f8f5c69e987c31bf016eca4a38dba46f0.tar.xz linux-df15929f8f5c69e987c31bf016eca4a38dba46f0.zip | |
Merge branch 'linus' into x86/microcode, to pick up merge window changes
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/kernel/cpu/intel.c')
| -rw-r--r-- | arch/x86/kernel/cpu/intel.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 6e2ffbebbcdb..c1a89bc026ac 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -300,15 +300,14 @@ static void intel_workarounds(struct cpuinfo_x86 *c) } /* - * P4 Xeon errata 037 workaround. + * P4 Xeon erratum 037 workaround. * Hardware prefetcher may cause stale data to be loaded into the cache. */ if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) { if (msr_set_bit(MSR_IA32_MISC_ENABLE, - MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) - > 0) { + MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) { pr_info("CPU: C0 stepping P4 Xeon detected.\n"); - pr_info("CPU: Disabling hardware prefetching (Errata 037)\n"); + pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n"); } } |