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| author | Jan Beulich <jbeulich@novell.com> | 2009-03-12 13:37:34 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2009-03-13 02:37:17 +0100 |
| commit | 13c6c53282d99c82e79b02477efd2c1e30a991ef (patch) | |
| tree | 71c7b82f94e23ead15f49e4081937bd8d748cef5 /arch/x86/kernel/cpu/intel.c | |
| parent | x86, 32-bit: also limit NODES_HIGH_SHIFT here (diff) | |
| download | linux-13c6c53282d99c82e79b02477efd2c1e30a991ef.tar.xz linux-13c6c53282d99c82e79b02477efd2c1e30a991ef.zip | |
x86, 32-bit: also use cpuinfo_x86's x86_{phys,virt}_bits members
Impact: 32/64-bit consolidation
In a first step, this allows fixing phys_addr_valid() for PAE (which
until now reported all addresses to be valid). Subsequently, this will
also allow simplifying some MTRR handling code.
Signed-off-by: Jan Beulich <jbeulich@novell.com>
LKML-Reference: <49B9101E.76E4.0078.0@novell.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/cpu/intel.c')
| -rw-r--r-- | arch/x86/kernel/cpu/intel.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 191117f1ad51..ae769471042e 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -54,6 +54,11 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) c->x86_cache_alignment = 128; #endif + /* CPUID workaround for 0F33/0F34 CPU */ + if (c->x86 == 0xF && c->x86_model == 0x3 + && (c->x86_mask == 0x3 || c->x86_mask == 0x4)) + c->x86_phys_bits = 36; + /* * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate * with P/T states and does not stop in deep C-states |