diff options
| author | Pallipadi, Venkatesh <venkatesh.pallipadi@intel.com> | 2009-12-17 21:27:02 +0100 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2009-12-17 23:44:35 +0100 |
| commit | 6c56ccecf05fafe100ab4ea94f6fccbf5ff00db7 (patch) | |
| tree | c9d1f27a2fbb53251d2abeeab771b86d4122541a /arch/x86/kernel/cpu/intel.c | |
| parent | x86: Don't use POSIX character classes in gen-insn-attr-x86.awk (diff) | |
| download | linux-6c56ccecf05fafe100ab4ea94f6fccbf5ff00db7.tar.xz linux-6c56ccecf05fafe100ab4ea94f6fccbf5ff00db7.zip | |
x86: Reenable TSC sync check at boot, even with NONSTOP_TSC
Commit 83ce4009 did the following change
If the TSC is constant and non-stop, also set it reliable.
But, there seems to be few systems that will end up with TSC warp across
sockets, depending on how the cpus come out of reset. Skipping TSC sync
test on such systems may result in time inconsistency later.
So, reenable TSC sync test even on constant and non-stop TSC systems.
Set, sched_clock_stable to 1 by default and reset it in
mark_tsc_unstable, if TSC sync fails.
This change still gives perf benefit mentioned in 83ce4009 for systems
where TSC is reliable.
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Acked-by: Suresh Siddha <suresh.b.siddha@intel.com>
LKML-Reference: <20091217202702.GA18015@linux-os.sc.intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/kernel/cpu/intel.c')
| -rw-r--r-- | arch/x86/kernel/cpu/intel.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 9c31e8b09d2c..879666f4d871 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -70,7 +70,6 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) if (c->x86_power & (1 << 8)) { set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); - set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE); sched_clock_stable = 1; } |