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| author | Andreas Herrmann <andreas.herrmann3@amd.com> | 2010-09-17 18:02:54 +0200 |
|---|---|---|
| committer | H. Peter Anvin <hpa@linux.intel.com> | 2010-09-17 22:26:21 +0200 |
| commit | 900f9ac9f12dc3dd6fc8e33e16df172eafcaead6 (patch) | |
| tree | 7fb7bf3a150f8a3cc513e1bf6bd842e4ad213473 /arch/x86/kernel/cpu | |
| parent | x86, cacheinfo: Fix dependency of AMD L3 CID (diff) | |
| download | linux-900f9ac9f12dc3dd6fc8e33e16df172eafcaead6.tar.xz linux-900f9ac9f12dc3dd6fc8e33e16df172eafcaead6.zip | |
x86, k8-gart: Decouple handling of garts and northbridges
So far we only provide num_k8_northbridges. This is required in
different areas (e.g. L3 cache index disable, GART). But not all AMD
CPUs provide a GART. Thus it is useful to split off the GART handling
from the generic caching of AMD northbridge misc devices.
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
LKML-Reference: <20100917160254.GC4958@loge.amd.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch/x86/kernel/cpu')
| -rw-r--r-- | arch/x86/kernel/cpu/intel_cacheinfo.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index 2521cdcb877e..6fdfb0b20f8c 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c @@ -369,7 +369,7 @@ static void __cpuinit amd_check_l3_disable(struct _cpuid4_info_regs *this_leaf, return; /* not in virtualized environments */ - if (num_k8_northbridges == 0) + if (k8_northbridges.num == 0) return; /* @@ -377,7 +377,7 @@ static void __cpuinit amd_check_l3_disable(struct _cpuid4_info_regs *this_leaf, * never freed but this is done only on shutdown so it doesn't matter. */ if (!l3_caches) { - int size = num_k8_northbridges * sizeof(struct amd_l3_cache *); + int size = k8_northbridges.num * sizeof(struct amd_l3_cache *); l3_caches = kzalloc(size, GFP_ATOMIC); if (!l3_caches) |