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authorTorgue Alexandre <alexandre.torgue@st.com>2016-08-31 10:14:14 +0200
committerRussell King <rmk+kernel@armlinux.org.uk>2016-09-06 16:51:09 +0200
commit8e02676ffa6906a97de7f90772e9cdcb75ea6743 (patch)
tree56f3f1c122b4a9218eedd45d952211377b96a5a0 /arch/x86/kernel/smpboot.c
parentARM: 8609/1: V7M: Add support for the Cortex-M7 processor (diff)
downloadlinux-8e02676ffa6906a97de7f90772e9cdcb75ea6743.tar.xz
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ARM: 8610/1: V7M: Add dsb before jumping in handler mode
According to ARM AN321 (section 4.12): "If the vector table is in writable memory such as SRAM, either relocated by VTOR or a device dependent memory remapping mechanism, then architecturally a memory barrier instruction is required after the vector table entry is updated, and if the exception is to be activated immediately" Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/x86/kernel/smpboot.c')
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