diff options
| author | Glauber de Oliveira Costa <gcosta@redhat.com> | 2008-03-19 18:25:28 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-04-17 17:41:01 +0200 |
| commit | 693d4b8a6429af7f2029df20a59e22f4d752e141 (patch) | |
| tree | 512a24d553a31eedb5aa69a1382c861c13491ac5 /arch/x86/kernel/smpboot_32.c | |
| parent | x86: allow user to impress friends. (diff) | |
| download | linux-693d4b8a6429af7f2029df20a59e22f4d752e141.tar.xz linux-693d4b8a6429af7f2029df20a59e22f4d752e141.zip | |
x86: do smp tainting checks in a separate function
It will ease integration for x86_64
Signed-off-by: Glauber Costa <gcosta@redhat.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/smpboot_32.c')
| -rw-r--r-- | arch/x86/kernel/smpboot_32.c | 20 |
1 files changed, 2 insertions, 18 deletions
diff --git a/arch/x86/kernel/smpboot_32.c b/arch/x86/kernel/smpboot_32.c index 34493f8ba8ac..361851cdaa97 100644 --- a/arch/x86/kernel/smpboot_32.c +++ b/arch/x86/kernel/smpboot_32.c @@ -59,8 +59,6 @@ #include <asm/vmi.h> #include <asm/mtrr.h> -extern int smp_b_stepping; - static cpumask_t smp_commenced_mask; /* which logical CPU number maps to which CPU (physical APIC ID) */ @@ -791,6 +789,7 @@ static int __init smp_sanity_check(unsigned max_cpus) } extern void impress_friends(void); +extern void smp_checks(void); /* * Cycle through the processors sending APIC IPIs to boot each. */ @@ -865,22 +864,7 @@ static void __init smp_boot_cpus(unsigned int max_cpus) impress_friends(); - if (smp_b_stepping) - printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n"); - - /* - * Don't taint if we are running SMP kernel on a single non-MP - * approved Athlon - */ - if (tainted & TAINT_UNSAFE_SMP) { - if (cpus_weight(cpu_present_map)) - printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n"); - else - tainted &= ~TAINT_UNSAFE_SMP; - } - - Dprintk("Boot done.\n"); - + smp_checks(); /* * construct cpu_sibling_map, so that we can tell sibling CPUs * efficiently. |