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| author | Suresh Siddha <suresh.b.siddha@intel.com> | 2008-11-04 22:53:04 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-11-06 09:41:49 +0100 |
| commit | d6f0f39b7d05e62b347c4352d070e4afb3ade4b5 (patch) | |
| tree | f5f2e844e5674b1d572be2b6e54fb36e5540cbe3 /arch/x86/kernel/tlb_32.c | |
| parent | x86: remove VISWS and PARAVIRT around NR_IRQS puzzle (diff) | |
| download | linux-d6f0f39b7d05e62b347c4352d070e4afb3ade4b5.tar.xz linux-d6f0f39b7d05e62b347c4352d070e4afb3ade4b5.zip | |
x86: add smp_mb() before sending INVALIDATE_TLB_VECTOR
Impact: fix rare x2apic hang
On x86, x2apic mode accesses for sending IPI's don't have serializing
semantics. If the IPI receivner refers(in lock-free fashion) to some
memory setup by the sender, the need for smp_mb() before sending the
IPI becomes critical in x2apic mode.
Add the smp_mb() in native_flush_tlb_others() before sending the IPI.
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/tlb_32.c')
| -rw-r--r-- | arch/x86/kernel/tlb_32.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/x86/kernel/tlb_32.c b/arch/x86/kernel/tlb_32.c index e00534b33534..f4049f3513b6 100644 --- a/arch/x86/kernel/tlb_32.c +++ b/arch/x86/kernel/tlb_32.c @@ -154,6 +154,12 @@ void native_flush_tlb_others(const cpumask_t *cpumaskp, struct mm_struct *mm, flush_mm = mm; flush_va = va; cpus_or(flush_cpumask, cpumask, flush_cpumask); + + /* + * Make the above memory operations globally visible before + * sending the IPI. + */ + smp_mb(); /* * We have to send the IPI only to * CPUs affected. |