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| author | Thomas Gleixner <tglx@linutronix.de> | 2020-04-21 11:20:43 +0200 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2020-04-26 18:52:33 +0200 |
| commit | bfe3d8f6313d1e10806062ba22c5f660dddecbcc (patch) | |
| tree | 70576d7960c88d6888ad85729dd007217d838536 /arch/x86/mm/init.c | |
| parent | xen/privcmd: Remove unneeded asm/tlb.h include (diff) | |
| download | linux-bfe3d8f6313d1e10806062ba22c5f660dddecbcc.tar.xz linux-bfe3d8f6313d1e10806062ba22c5f660dddecbcc.zip | |
x86/tlb: Restrict access to tlbstate
Hide tlbstate, flush_tlb_info and related helpers when tlbflush.h is
included from a module. Modules have absolutely no business with these
internals.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Alexandre Chartre <alexandre.chartre@oracle.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200421092600.328438734@linutronix.de
Diffstat (limited to 'arch/x86/mm/init.c')
| -rw-r--r-- | arch/x86/mm/init.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index d37e8164022e..248dc8fe43c5 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -992,7 +992,6 @@ __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate) = { .next_asid = 1, .cr4 = ~0UL, /* fail hard if we screw up cr4 shadow initialization */ }; -EXPORT_PER_CPU_SYMBOL(cpu_tlbstate); void update_cache_mode_entry(unsigned entry, enum page_cache_mode cache) { |