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| author | Andreas Herrmann <andreas.herrmann3@amd.com> | 2011-12-05 18:12:28 +0100 |
|---|---|---|
| committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2012-01-06 21:10:48 +0100 |
| commit | ca3671a83389eea1458929d22c66a69e955bfb07 (patch) | |
| tree | 5e1305545d08154e9d7a7f2e1af0dd04eacc9ab6 /arch/x86/pci/amd_bus.c | |
| parent | PCI: latency timer doesn't apply to PCIe (diff) | |
| download | linux-ca3671a83389eea1458929d22c66a69e955bfb07.tar.xz linux-ca3671a83389eea1458929d22c66a69e955bfb07.zip | |
x86/PCI: amd: Kill misleading message about enablement of IO access to PCI ECS]
Commit 24d9b70b8c679264756a6980e668b96b3f964826 (x86: Use PCI method
for enabling AMD extended config space before MSR method) added a
message when IO access to PCI ECS was enabled via access to the NB_CFG
PCI register. This can lead to a bogus message like
[ 0.365177] Extended Config Space enabled on 0 nodes
which is misleading because IO ECS access is subsequently enabled for
AMD CPUs (that support this) by modifying the corresponding NB_CFG
MSR.
Furthermore it's not "Extended Config Space" that is enabled by this
register setting. It's the IO access that is enabled for extended
configruation space.
IMHO the ambiguous message needs to be cancelled.
Cc: Jan Beulich <jbeulich@novell.com>
Cc: Robert Richter <robert.richter@amd.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'arch/x86/pci/amd_bus.c')
| -rw-r--r-- | arch/x86/pci/amd_bus.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c index 026e4931d162..7b7a89712d50 100644 --- a/arch/x86/pci/amd_bus.c +++ b/arch/x86/pci/amd_bus.c @@ -403,7 +403,6 @@ static void __init pci_enable_pci_io_ecs(void) ++n; } } - pr_info("Extended Config Space enabled on %u nodes\n", n); #endif } |