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author | Linus Torvalds <torvalds@linux-foundation.org> | 2019-11-30 23:49:08 +0100 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2019-11-30 23:49:08 +0100 |
commit | 8fa91bfa9ba4060347c45673f8ee990a2a1d760e (patch) | |
tree | 977e9b41198f7ae3a06338926cacad3dd0b5b839 /arch/x86 | |
parent | Merge branch 'parisc-5.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/... (diff) | |
parent | x86/mce/therm_throt: Mask out read-only and reserved MSR bits (diff) | |
download | linux-8fa91bfa9ba4060347c45673f8ee990a2a1d760e.tar.xz linux-8fa91bfa9ba4060347c45673f8ee990a2a1d760e.zip |
Merge branch 'ras-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull RAS fix from Borislav Petkov:
"One urgent fix for the thermal throttling machinery: the recent change
reworking the thermal notifications forgot to mask out read-only and
reserved bits in the thermal status MSRs, leading to exceptions while
writing those MSRs.
The fix takes care of masking out those bits first"
* 'ras-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/mce/therm_throt: Mask out read-only and reserved MSR bits
Diffstat (limited to 'arch/x86')
-rw-r--r-- | arch/x86/kernel/cpu/mce/therm_throt.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/arch/x86/kernel/cpu/mce/therm_throt.c b/arch/x86/kernel/cpu/mce/therm_throt.c index d01e0da0163a..b38010b541d6 100644 --- a/arch/x86/kernel/cpu/mce/therm_throt.c +++ b/arch/x86/kernel/cpu/mce/therm_throt.c @@ -195,17 +195,24 @@ static const struct attribute_group thermal_attr_group = { #define THERM_THROT_POLL_INTERVAL HZ #define THERM_STATUS_PROCHOT_LOG BIT(1) +#define THERM_STATUS_CLEAR_CORE_MASK (BIT(1) | BIT(3) | BIT(5) | BIT(7) | BIT(9) | BIT(11) | BIT(13) | BIT(15)) +#define THERM_STATUS_CLEAR_PKG_MASK (BIT(1) | BIT(3) | BIT(5) | BIT(7) | BIT(9) | BIT(11)) + static void clear_therm_status_log(int level) { int msr; - u64 msr_val; + u64 mask, msr_val; - if (level == CORE_LEVEL) - msr = MSR_IA32_THERM_STATUS; - else - msr = MSR_IA32_PACKAGE_THERM_STATUS; + if (level == CORE_LEVEL) { + msr = MSR_IA32_THERM_STATUS; + mask = THERM_STATUS_CLEAR_CORE_MASK; + } else { + msr = MSR_IA32_PACKAGE_THERM_STATUS; + mask = THERM_STATUS_CLEAR_PKG_MASK; + } rdmsrl(msr, msr_val); + msr_val &= mask; wrmsrl(msr, msr_val & ~THERM_STATUS_PROCHOT_LOG); } |