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| author | Len Brown <len.brown@intel.com> | 2012-11-01 01:47:40 +0100 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2012-11-24 03:40:11 +0100 |
| commit | 3fc808aaa052dec7b155f3242c6c0eabf0c49127 (patch) | |
| tree | fd445d7caba56ae094b6ca99797bff50ad69fe59 /arch/x86 | |
| parent | tools/power/x86/turbostat: share kernel MSR #defines (diff) | |
| download | linux-3fc808aaa052dec7b155f3242c6c0eabf0c49127.tar.xz linux-3fc808aaa052dec7b155f3242c6c0eabf0c49127.zip | |
x86 power: define RAPL MSRs
The Run Time Average Power Limiting interface
is currently model specific, present on Sandy Bridge
and Ivy Bridge processors.
These #defines correspond to documentation in the latest
"Intel® 64 and IA-32 Architectures Software Developer Manual",
plus some typos in that document corrected.
Signed-off-by: Len Brown <len.brown@intel.com>
Cc: x86@kernel.org
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/include/asm/msr-index.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 2639f816628e..4a4abaea04d6 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -117,6 +117,29 @@ #define MSR_CORE_C7_RESIDENCY 0x000003fe #define MSR_PKG_C2_RESIDENCY 0x0000060d +/* Run Time Average Power Limiting (RAPL) Interface */ + +#define MSR_RAPL_POWER_UNIT 0x00000606 + +#define MSR_PKG_POWER_LIMIT 0x00000610 +#define MSR_PKG_ENERGY_STATUS 0x00000611 +#define MSR_PKG_PERF_STATUS 0x00000613 +#define MSR_PKG_POWER_INFO 0x00000614 + +#define MSR_DRAM_POWER_LIMIT 0x00000618 +#define MSR_DRAM_ENERGY_STATUS 0x00000619 +#define MSR_DRAM_PERF_STATUS 0x0000061b +#define MSR_DRAM_POWER_INFO 0x0000061c + +#define MSR_PP0_POWER_LIMIT 0x00000638 +#define MSR_PP0_ENERGY_STATUS 0x00000639 +#define MSR_PP0_POLICY 0x0000063a +#define MSR_PP0_PERF_STATUS 0x0000063b + +#define MSR_PP1_POWER_LIMIT 0x00000640 +#define MSR_PP1_ENERGY_STATUS 0x00000641 +#define MSR_PP1_POLICY 0x00000642 + #define MSR_AMD64_MC0_MASK 0xc0010044 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) |