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| author | Stephane Eranian <eranian@hpl.hp.com> | 2006-12-07 02:14:11 +0100 |
|---|---|---|
| committer | Andi Kleen <andi@basil.nowhere.org> | 2006-12-07 02:14:11 +0100 |
| commit | ee58fad51a2a767cb2567706ace967705233d881 (patch) | |
| tree | b87f182688a0ffb3b60f78637f391e69c59d1e59 /arch/x86_64/kernel/setup.c | |
| parent | [PATCH] i386: Make irq_vector static (diff) | |
| download | linux-ee58fad51a2a767cb2567706ace967705233d881.tar.xz linux-ee58fad51a2a767cb2567706ace967705233d881.zip | |
[PATCH] x86-64: x86-64 add Intel BTS cpufeature bit and detection (take 2)
Here is a small patch for x86-64 which adds a cpufeature flag and
detection code for Intel's Branch Trace Store (BTS) feature. This
feature can be found on Intel P4 and Core 2 processors among others.
It can also be used by perfmon.
changelog:
- add CPU_FEATURE_BTS
- add Branch Trace Store detection
signed-off-by: stephane eranian <eranian@hpl.hp.com>
Signed-off-by: Andi Kleen <ak@suse.de>
Diffstat (limited to 'arch/x86_64/kernel/setup.c')
| -rw-r--r-- | arch/x86_64/kernel/setup.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86_64/kernel/setup.c b/arch/x86_64/kernel/setup.c index 619af2e2fa26..a570c81c8316 100644 --- a/arch/x86_64/kernel/setup.c +++ b/arch/x86_64/kernel/setup.c @@ -838,6 +838,8 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) if (cpu_has_ds) { unsigned int l1, l2; rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); + if (!(l1 & (1<<11))) + set_bit(X86_FEATURE_BTS, c->x86_capability); if (!(l1 & (1<<12))) set_bit(X86_FEATURE_PEBS, c->x86_capability); } |