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| author | Marc Zyngier <marc.zyngier@arm.com> | 2019-07-22 15:53:09 +0200 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2019-07-22 16:24:16 +0200 |
| commit | cbdf8a189a66001c36007bf0f5c975d0376c5c3a (patch) | |
| tree | 04692e85f7d27e7ff4c6c07aed2905a1d6b7112d /arch/xtensa/configs | |
| parent | MAINTAINERS: Update my email address (diff) | |
| download | linux-cbdf8a189a66001c36007bf0f5c975d0376c5c3a.tar.xz linux-cbdf8a189a66001c36007bf0f5c975d0376c5c3a.zip | |
arm64: Force SSBS on context switch
On a CPU that doesn't support SSBS, PSTATE[12] is RES0. In a system
where only some of the CPUs implement SSBS, we end-up losing track of
the SSBS bit across task migration.
To address this issue, let's force the SSBS bit on context switch.
Fixes: 8f04e8e6e29c ("arm64: ssbd: Add support for PSTATE.SSBS rather than trapping to EL3")
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
[will: inverted logic and added comments]
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/xtensa/configs')
0 files changed, 0 insertions, 0 deletions