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authorMax Filippov <jcmvbkbc@gmail.com>2016-06-29 03:18:45 +0200
committerMax Filippov <jcmvbkbc@gmail.com>2016-06-29 03:18:45 +0200
commit8a5043b68320aa880d46744ab40915bee8939882 (patch)
treeb1874c8ce0fe23b6705049daeea14fbf65742c87 /arch/xtensa/include
parentLinux 4.7-rc4 (diff)
downloadlinux-8a5043b68320aa880d46744ab40915bee8939882.tar.xz
linux-8a5043b68320aa880d46744ab40915bee8939882.zip
xtensa: define ___unlock_[di]cache_all unconditionally
Provide macro definitions regardless of whether caches are lockable or not, make definitions empty in latter case. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'arch/xtensa/include')
-rw-r--r--arch/xtensa/include/asm/cacheasm.h11
1 files changed, 4 insertions, 7 deletions
diff --git a/arch/xtensa/include/asm/cacheasm.h b/arch/xtensa/include/asm/cacheasm.h
index e0f9e1109c83..2041abb10a23 100644
--- a/arch/xtensa/include/asm/cacheasm.h
+++ b/arch/xtensa/include/asm/cacheasm.h
@@ -69,26 +69,23 @@
.endm
-#if XCHAL_DCACHE_LINE_LOCKABLE
-
.macro ___unlock_dcache_all ar at
-#if XCHAL_DCACHE_SIZE
+#if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE
__loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
#endif
.endm
-#endif
-
-#if XCHAL_ICACHE_LINE_LOCKABLE
.macro ___unlock_icache_all ar at
+#if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE
__loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH
+#endif
.endm
-#endif
+
.macro ___flush_invalidate_dcache_all ar at