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authorMax Filippov <jcmvbkbc@gmail.com>2015-08-25 08:04:12 +0200
committerChris Zankel <chris@zankel.net>2016-03-11 09:53:31 +0100
commitd99434e1760b94e08512821b5a05992398c1aa9e (patch)
treee2f871abcee6bf67825251a124fb8da5a813fd31 /arch/xtensa
parentxtensa: xtfpga: fix serial port register width and endianness (diff)
downloadlinux-d99434e1760b94e08512821b5a05992398c1aa9e.tar.xz
linux-d99434e1760b94e08512821b5a05992398c1aa9e.zip
xtensa: xtfpga: fix ethernet controller endianness
Ethernet controller is attached to XTFPGA boards as native endian device, mark it as such in DTS and pass correct endianness in platform data. This makes network functional on big-endian CPUs. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'arch/xtensa')
-rw-r--r--arch/xtensa/boot/dts/xtfpga.dtsi1
-rw-r--r--arch/xtensa/platforms/xtfpga/setup.c1
2 files changed, 2 insertions, 0 deletions
diff --git a/arch/xtensa/boot/dts/xtfpga.dtsi b/arch/xtensa/boot/dts/xtfpga.dtsi
index be3fd769677a..de133badcdc9 100644
--- a/arch/xtensa/boot/dts/xtfpga.dtsi
+++ b/arch/xtensa/boot/dts/xtfpga.dtsi
@@ -69,6 +69,7 @@
enet0: ethoc@0d030000 {
compatible = "opencores,ethoc";
reg = <0x0d030000 0x4000 0x0d800000 0x4000>;
+ native-endian;
interrupts = <1 1>; /* external irq 1 */
local-mac-address = [00 50 c2 13 6f 00];
clocks = <&osc>;
diff --git a/arch/xtensa/platforms/xtfpga/setup.c b/arch/xtensa/platforms/xtfpga/setup.c
index b7f468a6a557..b509d1f55ed5 100644
--- a/arch/xtensa/platforms/xtfpga/setup.c
+++ b/arch/xtensa/platforms/xtfpga/setup.c
@@ -223,6 +223,7 @@ static struct ethoc_platform_data ethoc_pdata = {
*/
.hwaddr = { 0x00, 0x50, 0xc2, 0x13, 0x6f, 0 },
.phy_id = -1,
+ .big_endian = XCHAL_HAVE_BE,
};
static struct platform_device ethoc_device = {