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| author | Thor Thayer <tthayer@opensource.altera.com> | 2016-02-10 20:26:23 +0100 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2016-02-11 12:32:11 +0100 |
| commit | 4d1138380ed6f1cca622e7de8bcc877c04a52d0d (patch) | |
| tree | 44625a01cd4507dfb90c728c299700b5d4726c7f /arch/xtensa | |
| parent | ARM: dts: Add Altera L2 Cache and OCRAM EDAC entries (diff) | |
| download | linux-4d1138380ed6f1cca622e7de8bcc877c04a52d0d.tar.xz linux-4d1138380ed6f1cca622e7de8bcc877c04a52d0d.zip | |
ARM: socfpga: Enable L2 cache ECC on startup
Enable ECC for L2 cache on machine startup. The ECC has to be enabled
before data is stored in memory otherwise the ECC will fail on reads.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: devicetree@vger.kernel.org
Cc: galak@codeaurora.org
Cc: grant.likely@linaro.org
Cc: ijc+devicetree@hellion.org.uk
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-doc@vger.kernel.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: mark.rutland@arm.com
Cc: m.chehab@samsung.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: Russell King <linux@arm.linux.org.uk>
Link: http://lkml.kernel.org/r/1455132384-17108-3-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'arch/xtensa')
0 files changed, 0 insertions, 0 deletions