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authorDavid Brownell <dbrownell@users.sourceforge.net>2009-04-22 04:58:13 +0200
committerDavid Woodhouse <David.Woodhouse@intel.com>2009-06-05 18:39:36 +0200
commit6a4123e581b3112ff4ea7439ab9ae5cb271a9dbd (patch)
tree29967a656e87ca5ca566006e47882cb2077ae14c /arch
parentmtd: nand: minor davinci_nand cleanup (diff)
downloadlinux-6a4123e581b3112ff4ea7439ab9ae5cb271a9dbd.tar.xz
linux-6a4123e581b3112ff4ea7439ab9ae5cb271a9dbd.zip
mtd: nand: davinci_nand, 4-bit ECC for smallpage
Minimal support for the 4-bit ECC engine found on DM355, DM365, DA830/OMAP-L137, and similar recent DaVinci-family chips. This is limited to small-page flash for now; there are some page layout issues for large page chips. Note that most boards using this engine (like the DM355 EVM) include 2GiB large page chips. Sanity tested on DM355 EVM after swapping the socketed NAND for a small-page one. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-davinci/include/mach/nand.h8
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/arch/arm/mach-davinci/include/mach/nand.h
index aa482841270b..b520c4b5678a 100644
--- a/arch/arm/mach-davinci/include/mach/nand.h
+++ b/arch/arm/mach-davinci/include/mach/nand.h
@@ -68,10 +68,14 @@ struct davinci_nand_pdata { /* platform_data */
/* none == NAND_ECC_NONE (strongly *not* advised!!)
* soft == NAND_ECC_SOFT
- * 1-bit == NAND_ECC_HW
- * 4-bit == NAND_ECC_HW_SYNDROME (not on all chips)
+ * else == NAND_ECC_HW, according to ecc_bits
+ *
+ * All DaVinci-family chips support 1-bit hardware ECC.
+ * Newer ones also support 4-bit ECC, but are awkward
+ * using it with large page chips.
*/
nand_ecc_modes_t ecc_mode;
+ u8 ecc_bits;
/* e.g. NAND_BUSWIDTH_16 or NAND_USE_FLASH_BBT */
unsigned options;