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authorNathan Lynch <ntl@pobox.com>2006-09-21 21:25:34 +0200
committerPaul Mackerras <paulus@samba.org>2006-09-22 07:19:58 +0200
commitd608df5c7da6ee968aa2ad43c596d5f8d4022299 (patch)
tree421df8cc60c8570e89b15a74cd67b177ca64778c /arch
parent[POWERPC] Fix IPIC pending register assignments (diff)
downloadlinux-d608df5c7da6ee968aa2ad43c596d5f8d4022299.tar.xz
linux-d608df5c7da6ee968aa2ad43c596d5f8d4022299.zip
[POWERPC] Maple U3 HT - reject inappropriate config space access
When there is a PCI-X mode 2 capable device behind the HT<->PCI-X bridge, the pci core decides that the device has the extended 4K config space, even though the bus is not operating in mode 2. This is because the u3_ht pci ops silently accept offsets greater than 255 but use only the 8 least significant bits, which means reading at offset 0x100 gets the data at offset 0x0, and causes confusion for lspci. Reject accesses to configuration space offsets greater than 255. Signed-off-by: Nathan Lynch <ntl@pobox.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/platforms/maple/pci.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/powerpc/platforms/maple/pci.c b/arch/powerpc/platforms/maple/pci.c
index dc05af5156a9..ec5c14f5ba49 100644
--- a/arch/powerpc/platforms/maple/pci.c
+++ b/arch/powerpc/platforms/maple/pci.c
@@ -213,6 +213,9 @@ static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
if (hose == NULL)
return PCIBIOS_DEVICE_NOT_FOUND;
+ if (offset > 0xff)
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+
addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
if (!addr)
return PCIBIOS_DEVICE_NOT_FOUND;
@@ -245,6 +248,9 @@ static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
if (hose == NULL)
return PCIBIOS_DEVICE_NOT_FOUND;
+ if (offset > 0xff)
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+
addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
if (!addr)
return PCIBIOS_DEVICE_NOT_FOUND;