diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2009-01-28 19:48:23 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2009-01-30 22:32:58 +0100 |
| commit | 42fe7ee31ff904b2419f02864938966c8f0b6edc (patch) | |
| tree | aeb78c763827b6ecdd2f5440eb1ae0258e5aa1ea /arch | |
| parent | MIPS: IP27: Switch from DMA_IP27 to DMA_COHERENT (diff) | |
| download | linux-42fe7ee31ff904b2419f02864938966c8f0b6edc.tar.xz linux-42fe7ee31ff904b2419f02864938966c8f0b6edc.zip | |
MIPS: R2: Fix broken installation of cache error handler.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/kernel/traps.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index f6083c6bfaa4..fa06460cbf2c 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1582,7 +1582,11 @@ void __init set_handler(unsigned long offset, void *addr, unsigned long size) static char panic_null_cerr[] __cpuinitdata = "Trying to set NULL cache error exception handler"; -/* Install uncached CPU exception handler */ +/* + * Install uncached CPU exception handler. + * This is suitable only for the cache error exception which is the only + * exception handler that is being run uncached. + */ void __cpuinit set_uncached_handler(unsigned long offset, void *addr, unsigned long size) { @@ -1593,7 +1597,7 @@ void __cpuinit set_uncached_handler(unsigned long offset, void *addr, unsigned long uncached_ebase = TO_UNCAC(ebase); #endif if (cpu_has_mips_r2) - ebase += (read_c0_ebase() & 0x3ffff000); + uncached_ebase += (read_c0_ebase() & 0x3ffff000); if (!addr) panic(panic_null_cerr); |