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| author | Paul Walmsley <paul@pwsan.com> | 2012-05-08 19:34:28 +0200 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2012-05-09 01:25:36 +0200 |
| commit | 45a4bb067c25355b5d362eb09fa97e51a2a519c8 (patch) | |
| tree | ba8ee2a3e0026cef43eb87508300c9608f95b2fd /arch | |
| parent | ARM: OMAP2+: hwmod data: add HDQ/1-wire hwmod shared data (diff) | |
| download | linux-45a4bb067c25355b5d362eb09fa97e51a2a519c8.tar.xz linux-45a4bb067c25355b5d362eb09fa97e51a2a519c8.zip | |
ARM: OMAP3: hwmod data: add HDQ/1-wire hwmod
Add the HDQ1W hwmod for OMAP34xx, OMAP36xx, and AM3505/3517 devices.
According to the respective TRMs, it doesn't appear to be available for the
816x/814x or the AM335x.
The OCPIF_SWSUP_IDLE flag is added to work around an apparent hardware
bug: the hardware is not taking the CM_FCLKEN*_CORE.EN_HDQ bit into
account when considering whether to go idle:
http://www.spinics.net/lists/linux-omap/msg63576.html
This causes HDQ transfers to fail or become corrupt. Thanks to
NeilBrown for his help diagnosing and testing fixes for this problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: NeilBrown <neilb@suse.de>
Tested-by: NeilBrown <neilb@suse.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 0c65079c2b69..97c65973ae7f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -1980,6 +1980,22 @@ static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { }, }; +static struct omap_hwmod omap3xxx_hdq1w_hwmod = { + .name = "hdq1w", + .mpu_irqs = omap2_hdq1w_mpu_irqs, + .main_clk = "hdq_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_HDQ_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT, + }, + }, + .class = &omap2_hdq1w_class, +}; + /* * interfaces */ @@ -3059,6 +3075,16 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_core -> hdq1w interface */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_hdq1w_hwmod, + .clk = "hdq_ick", + .addr = omap2_hdq1w_addr_space, + .user = OCP_USER_MPU | OCP_USER_SDMA, + .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, +}; + static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { &omap3xxx_l3_main__l4_core, &omap3xxx_l3_main__l4_per, @@ -3151,6 +3177,7 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { &omap34xx_l4_core__sr1, &omap34xx_l4_core__sr2, &omap3xxx_l4_core__mailbox, + &omap3xxx_l4_core__hdq1w, NULL }; @@ -3170,6 +3197,7 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { &omap3xxx_l4_core__usb_tll_hs, &omap3xxx_l4_core__es3plus_mmc1, &omap3xxx_l4_core__es3plus_mmc2, + &omap3xxx_l4_core__hdq1w, NULL }; |