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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-02-22 18:25:55 +0100 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-02-22 18:25:55 +0100 |
| commit | ee88347755460e8ceb37e8453adcf5fd7ca5ff00 (patch) | |
| tree | 6a604503807d1a342b4e58ffabe11bd2a26661ff /arch | |
| parent | Merge branch 'fix/asoc' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwa... (diff) | |
| parent | perf: Fix throttle logic (diff) | |
| download | linux-ee88347755460e8ceb37e8453adcf5fd7ca5ff00.tar.xz linux-ee88347755460e8ceb37e8453adcf5fd7ca5ff00.zip | |
Merge branch 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
perf: Fix throttle logic
perf, x86: P4 PMU: Fix spurious NMI messages
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/include/asm/perf_event_p4.h | 1 | ||||
| -rw-r--r-- | arch/x86/kernel/cpu/perf_event_p4.c | 11 |
2 files changed, 9 insertions, 3 deletions
diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h index e2f6a99f14ab..cc29086e30cd 100644 --- a/arch/x86/include/asm/perf_event_p4.h +++ b/arch/x86/include/asm/perf_event_p4.h @@ -22,6 +22,7 @@ #define ARCH_P4_CNTRVAL_BITS (40) #define ARCH_P4_CNTRVAL_MASK ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1) +#define ARCH_P4_UNFLAGGED_BIT ((1ULL) << (ARCH_P4_CNTRVAL_BITS - 1)) #define P4_ESCR_EVENT_MASK 0x7e000000U #define P4_ESCR_EVENT_SHIFT 25 diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c index f7a0993c1e7c..ff751a9f182b 100644 --- a/arch/x86/kernel/cpu/perf_event_p4.c +++ b/arch/x86/kernel/cpu/perf_event_p4.c @@ -770,9 +770,14 @@ static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc) return 1; } - /* it might be unflagged overflow */ - rdmsrl(hwc->event_base + hwc->idx, v); - if (!(v & ARCH_P4_CNTRVAL_MASK)) + /* + * In some circumstances the overflow might issue an NMI but did + * not set P4_CCCR_OVF bit. Because a counter holds a negative value + * we simply check for high bit being set, if it's cleared it means + * the counter has reached zero value and continued counting before + * real NMI signal was received: + */ + if (!(v & ARCH_P4_UNFLAGGED_BIT)) return 1; return 0; |