diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2012-05-14 15:59:18 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2012-05-14 17:35:50 +0200 |
| commit | 090a80cba39f2763a488b6f7c65e38922d5aa17a (patch) | |
| tree | ba3797eeca74c42be95bc592ed2db1be99e329d2 /arch | |
| parent | Linux 3.4-rc7 (diff) | |
| parent | pinctrl: SPEAr1310: Fix pin numbers for clcd_high_res (diff) | |
| download | linux-090a80cba39f2763a488b6f7c65e38922d5aa17a.tar.xz linux-090a80cba39f2763a488b6f7c65e38922d5aa17a.zip | |
Merge branch 'spear/13xx' into next/soc2
* spear/13xx:
pinctrl: SPEAr1310: Fix pin numbers for clcd_high_res
SPEAr: Update MAINTAINERS and Documentation
SPEAr13xx: Add defconfig
SPEAr13xx: Add compilation support
SPEAr13xx: Add dts and dtsi files
pinctrl: Add SPEAr13xx pinctrl drivers
pinctrl: SPEAr: Create macro for declaring GPIO PINS
SPEAr13xx: Add common clock framework support
SPEAr13xx: Add source files
SPEAr13xx: Add header files
Depends on clock, pinctrl and dt branches to go first.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch')
81 files changed, 5119 insertions, 5747 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 36586dba6fa6..75066ed1f649 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -980,6 +980,7 @@ config PLAT_SPEAR select ARM_AMBA select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP + select COMMON_CLK select CLKSRC_MMIO select GENERIC_CLOCKEVENTS select HAVE_CLK diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 047a20780fc1..2aa75b58bf12 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -192,6 +192,8 @@ machine-$(CONFIG_ARCH_VEXPRESS) := vexpress machine-$(CONFIG_ARCH_VT8500) := vt8500 machine-$(CONFIG_ARCH_W90X900) := w90x900 machine-$(CONFIG_FOOTBRIDGE) := footbridge +machine-$(CONFIG_MACH_SPEAR1310) := spear13xx +machine-$(CONFIG_MACH_SPEAR1340) := spear13xx machine-$(CONFIG_MACH_SPEAR300) := spear3xx machine-$(CONFIG_MACH_SPEAR310) := spear3xx machine-$(CONFIG_MACH_SPEAR320) := spear3xx diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts new file mode 100644 index 000000000000..8314e4171884 --- /dev/null +++ b/arch/arm/boot/dts/spear1310-evb.dts @@ -0,0 +1,292 @@ +/* + * DTS file for SPEAr1310 Evaluation Baord + * + * Copyright 2012 Viresh Kumar <viresh.kumar@st.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "spear1310.dtsi" + +/ { + model = "ST SPEAr1310 Evaluation Board"; + compatible = "st,spear1310-evb", "st,spear1310"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + reg = <0 0x40000000>; + }; + + ahb { + pinmux@e0700000 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + i2c0-pmx { + st,pins = "i2c0_grp"; + st,function = "i2c0"; + }; + i2s1 { + st,pins = "i2s1_grp"; + st,function = "i2s1"; + }; + gpio { + st,pins = "arm_gpio_grp"; + st,function = "arm_gpio"; + }; + eth { + st,pins = "gmii_grp"; + st,function = "gmii"; + }; + ssp0 { + st,pins = "ssp0_grp"; + st,function = "ssp0"; + }; + kbd { + st,pins = "keyboard_6x6_grp"; + st,function = "keyboard"; + }; + sdhci { + st,pins = "sdhci_grp"; + st,function = "sdhci"; + }; + smi-pmx { + st,pins = "smi_2_chips_grp"; + st,function = "smi"; + }; + uart0 { + st,pins = "uart0_grp"; + st,function = "uart0"; + }; + rs485 { + st,pins = "rs485_0_1_tdm_0_1_grp"; + st,function = "rs485_0_1_tdm_0_1"; + }; + i2c1_2 { + st,pins = "i2c_1_2_grp"; + st,function = "i2c_1_2"; + }; + pci { + st,pins = "pcie0_grp","pcie1_grp", + "pcie2_grp"; + st,function = "pci"; + }; + smii { + st,pins = "smii_0_1_2_grp"; + st,function = "smii_0_1_2"; + }; + nand { + st,pins = "nand_8bit_grp", + "nand_16bit_grp"; + st,function = "nand"; + }; + }; + }; + + ahci@b1000000 { + status = "okay"; + }; + + cf@b2800000 { + status = "okay"; + }; + + dma@ea800000 { + status = "okay"; + }; + + dma@eb000000 { + status = "okay"; + }; + + fsmc: flash@b0000000 { + status = "okay"; + }; + + gmac0: eth@e2000000 { + status = "okay"; + }; + + sdhci@b3000000 { + status = "okay"; + }; + + smi: flash@ea000000 { + status = "okay"; + clock-rate=<50000000>; + + flash@e6000000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xe6000000 0x800000>; + st,smi-fast-mode; + + partition@0 { + label = "xloader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "u-boot"; + reg = <0x10000 0x40000>; + }; + partition@50000 { + label = "linux"; + reg = <0x50000 0x2c0000>; + }; + partition@310000 { + label = "rootfs"; + reg = <0x310000 0x4f0000>; + }; + }; + }; + + spi0: spi@e0100000 { + status = "okay"; + }; + + ehci@e4800000 { + status = "okay"; + }; + + ehci@e5800000 { + status = "okay"; + }; + + ohci@e4000000 { + status = "okay"; + }; + + ohci@e5000000 { + status = "okay"; + }; + + apb { + adc@e0080000 { + status = "okay"; + }; + + gpio0: gpio@e0600000 { + status = "okay"; + }; + + gpio1: gpio@e0680000 { + status = "okay"; + }; + + i2c0: i2c@e0280000 { + status = "okay"; + }; + + i2c1: i2c@5cd00000 { + status = "okay"; + }; + + kbd@e0300000 { + linux,keymap = < 0x00000001 + 0x00010002 + 0x00020003 + 0x00030004 + 0x00040005 + 0x00050006 + 0x00060007 + 0x00070008 + 0x00080009 + 0x0100000a + 0x0101000c + 0x0102000d + 0x0103000e + 0x0104000f + 0x01050010 + 0x01060011 + 0x01070012 + 0x01080013 + 0x02000014 + 0x02010015 + 0x02020016 + 0x02030017 + 0x02040018 + 0x02050019 + 0x0206001a + 0x0207001b + 0x0208001c + 0x0300001d + 0x0301001e + 0x0302001f + 0x03030020 + 0x03040021 + 0x03050022 + 0x03060023 + 0x03070024 + 0x03080025 + 0x04000026 + 0x04010027 + 0x04020028 + 0x04030029 + 0x0404002a + 0x0405002b + 0x0406002c + 0x0407002d + 0x0408002e + 0x0500002f + 0x05010030 + 0x05020031 + 0x05030032 + 0x05040033 + 0x05050034 + 0x05060035 + 0x05070036 + 0x05080037 + 0x06000038 + 0x06010039 + 0x0602003a + 0x0603003b + 0x0604003c + 0x0605003d + 0x0606003e + 0x0607003f + 0x06080040 + 0x07000041 + 0x07010042 + 0x07020043 + 0x07030044 + 0x07040045 + 0x07050046 + 0x07060047 + 0x07070048 + 0x07080049 + 0x0800004a + 0x0801004b + 0x0802004c + 0x0803004d + 0x0804004e + 0x0805004f + 0x08060050 + 0x08070051 + 0x08080052 >; + autorepeat; + st,mode = <0>; + status = "okay"; + }; + + rtc@e0580000 { + status = "okay"; + }; + + serial@e0000000 { + status = "okay"; + }; + + wdt@ec800620 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi new file mode 100644 index 000000000000..9e61da404d57 --- /dev/null +++ b/arch/arm/boot/dts/spear1310.dtsi @@ -0,0 +1,184 @@ +/* + * DTS file for all SPEAr1310 SoCs + * + * Copyright 2012 Viresh Kumar <viresh.kumar@st.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "spear13xx.dtsi" + +/ { + compatible = "st,spear1310"; + + ahb { + ahci@b1000000 { + compatible = "snps,spear-ahci"; + reg = <0xb1000000 0x10000>; + interrupts = <0 68 0x4>; + status = "disabled"; + }; + + ahci@b1800000 { + compatible = "snps,spear-ahci"; + reg = <0xb1800000 0x10000>; + interrupts = <0 69 0x4>; + status = "disabled"; + }; + + ahci@b4000000 { + compatible = "snps,spear-ahci"; + reg = <0xb4000000 0x10000>; + interrupts = <0 70 0x4>; + status = "disabled"; + }; + + gmac1: eth@5c400000 { + compatible = "st,spear600-gmac"; + reg = <0x5c400000 0x8000>; + interrupts = <0 95 0x4>; + interrupt-names = "macirq"; + status = "disabled"; + }; + + gmac2: eth@5c500000 { + compatible = "st,spear600-gmac"; + reg = <0x5c500000 0x8000>; + interrupts = <0 96 0x4>; + interrupt-names = "macirq"; + status = "disabled"; + }; + + gmac3: eth@5c600000 { + compatible = "st,spear600-gmac"; + reg = <0x5c600000 0x8000>; + interrupts = <0 97 0x4>; + interrupt-names = "macirq"; + status = "disabled"; + }; + + gmac4: eth@5c700000 { + compatible = "st,spear600-gmac"; + reg = <0x5c700000 0x8000>; + interrupts = <0 98 0x4>; + interrupt-names = "macirq"; + status = "disabled"; + }; + + spi1: spi@5d400000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x5d400000 0x1000>; + interrupts = <0 99 0x4>; + status = "disabled"; + }; + + apb { + i2c1: i2c@5cd00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x5cd00000 0x1000>; + interrupts = <0 87 0x4>; + status = "disabled"; + }; + + i2c2: i2c@5ce00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x5ce00000 0x1000>; + interrupts = <0 88 0x4>; + status = "disabled"; + }; + + i2c3: i2c@5cf00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x5cf00000 0x1000>; + interrupts = <0 89 0x4>; + status = "disabled"; + }; + + i2c4: i2c@5d000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x5d000000 0x1000>; + interrupts = <0 90 0x4>; + status = "disabled"; + }; + + i2c5: i2c@5d100000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x5d100000 0x1000>; + interrupts = <0 91 0x4>; + status = "disabled"; + }; + + i2c6: i2c@5d200000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x5d200000 0x1000>; + interrupts = <0 92 0x4>; + status = "disabled"; + }; + + i2c7: i2c@5d300000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x5d300000 0x1000>; + interrupts = <0 93 0x4>; + status = "disabled"; + }; + + serial@5c800000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x5c800000 0x1000>; + interrupts = <0 82 0x4>; + status = "disabled"; + }; + + serial@5c900000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x5c900000 0x1000>; + interrupts = <0 83 0x4>; + status = "disabled"; + }; + + serial@5ca00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x5ca00000 0x1000>; + interrupts = <0 84 0x4>; + status = "disabled"; + }; + + serial@5cb00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x5cb00000 0x1000>; + interrupts = <0 85 0x4>; + status = "disabled"; + }; + + serial@5cc00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x5cc00000 0x1000>; + interrupts = <0 86 0x4>; + status = "disabled"; + }; + + thermal@e07008c4 { + st,thermal-flags = <0x7000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts new file mode 100644 index 000000000000..0d8472e5ab9f --- /dev/null +++ b/arch/arm/boot/dts/spear1340-evb.dts @@ -0,0 +1,308 @@ +/* + * DTS file for SPEAr1340 Evaluation Baord + * + * Copyright 2012 Viresh Kumar <viresh.kumar@st.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "spear1340.dtsi" + +/ { + model = "ST SPEAr1340 Evaluation Board"; + compatible = "st,spear1340-evb", "st,spear1340"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + reg = <0 0x40000000>; + }; + + ahb { + pinmux@e0700000 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + pads_as_gpio { + st,pins = "pads_as_gpio_grp"; + st,function = "pads_as_gpio"; + }; + fsmc { + st,pins = "fsmc_8bit_grp"; + st,function = "fsmc"; + }; + kbd { + st,pins = "keyboard_row_col_grp", + "keyboard_col5_grp"; + st,function = "keyboard"; + }; + uart0 { + st,pins = "uart0_grp", "uart0_enh_grp"; + st,function = "uart0"; + }; + i2c0-pmx { + st,pins = "i2c0_grp"; + st,function = "i2c0"; + }; + i2c1-pmx { + st,pins = "i2c1_grp"; + st,function = "i2c1"; + }; + spdif-in { + st,pins = "spdif_in_grp"; + st,function = "spdif_in"; + }; + spdif-out { + st,pins = "spdif_out_grp"; + st,function = "spdif_out"; + }; + ssp0 { + st,pins = "ssp0_grp", "ssp0_cs1_grp", + "ssp0_cs3_grp"; + st,function = "ssp0"; + }; + pwm { + st,pins = "pwm2_grp", "pwm3_grp"; + st,function = "pwm"; + }; + smi-pmx { + st,pins = "smi_grp"; + st,function = "smi"; + }; + i2s { + st,pins = "i2s_in_grp", "i2s_out_grp"; + st,function = "i2s"; + }; + gmac { + st,pins = "gmii_grp", "rgmii_grp"; + st,function = "gmac"; + }; + cam3 { + st,pins = "cam3_grp"; + st,function = "cam3"; + }; + cec0 { + st,pins = "cec0_grp"; + st,function = "cec0"; + }; + cec1 { + st,pins = "cec1_grp"; + st,function = "cec1"; + }; + sdhci { + st,pins = "sdhci_grp"; + st,function = "sdhci"; + }; + clcd { + st,pins = "clcd_grp"; + st,function = "clcd"; + }; + sata { + st,pins = "sata_grp"; + st,function = "sata"; + }; + }; + }; + + dma@ea800000 { + status = "okay"; + }; + + dma@eb000000 { + status = "okay"; + }; + + fsmc: flash@b0000000 { + status = "okay"; + }; + + gmac0: eth@e2000000 { + status = "okay"; + }; + + sdhci@b3000000 { + status = "okay"; + }; + + smi: flash@ea000000 { + status = "okay"; + clock-rate=<50000000>; + + flash@e6000000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xe6000000 0x800000>; + st,smi-fast-mode; + + partition@0 { + label = "xloader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "u-boot"; + reg = <0x10000 0x40000>; + }; + partition@50000 { + label = "linux"; + reg = <0x50000 0x2c0000>; + }; + partition@310000 { + label = "rootfs"; + reg = <0x310000 0x4f0000>; + }; + }; + }; + + spi0: spi@e0100000 { + status = "okay"; + }; + + ehci@e4800000 { + status = "okay"; + }; + + ehci@e5800000 { + status = "okay"; + }; + + ohci@e4000000 { + status = "okay"; + }; + + ohci@e5000000 { + status = "okay"; + }; + + apb { + adc@e0080000 { + status = "okay"; + }; + + gpio0: gpio@e0600000 { + status = "okay"; + }; + + gpio1: gpio@e0680000 { + status = "okay"; + }; + + i2c0: i2c@e0280000 { + status = "okay"; + }; + + i2c1: i2c@b4000000 { + status = "okay"; + }; + + kbd@e0300000 { + linux,keymap = < 0x00000001 + 0x00010002 + 0x00020003 + 0x00030004 + 0x00040005 + 0x00050006 + 0x00060007 + 0x00070008 + 0x00080009 + 0x0100000a + 0x0101000c + 0x0102000d + 0x0103000e + 0x0104000f + 0x01050010 + 0x01060011 + 0x01070012 + 0x01080013 + 0x02000014 + 0x02010015 + 0x02020016 + 0x02030017 + 0x02040018 + 0x02050019 + 0x0206001a + 0x0207001b + 0x0208001c + 0x0300001d + 0x0301001e + 0x0302001f + 0x03030020 + 0x03040021 + 0x03050022 + 0x03060023 + 0x03070024 + 0x03080025 + 0x04000026 + 0x04010027 + 0x04020028 + 0x04030029 + 0x0404002a + 0x0405002b + 0x0406002c + 0x0407002d + 0x0408002e + 0x0500002f + 0x05010030 + 0x05020031 + 0x05030032 + 0x05040033 + 0x05050034 + 0x05060035 + 0x05070036 + 0x05080037 + 0x06000038 + 0x06010039 + 0x0602003a + 0x0603003b + 0x0604003c + 0x0605003d + 0x0606003e + 0x0607003f + 0x06080040 + 0x07000041 + 0x07010042 + 0x07020043 + 0x07030044 + 0x07040045 + 0x07050046 + 0x07060047 + 0x07070048 + 0x07080049 + 0x0800004a + 0x0801004b + 0x0802004c + 0x0803004d + 0x0804004e + 0x0805004f + 0x08060050 + 0x08070051 + 0x08080052 >; + autorepeat; + st,mode = <0>; + status = "okay"; + }; + + rtc@e0580000 { + status = "okay"; + }; + + serial@e0000000 { + status = "okay"; + }; + + serial@b4100000 { + status = "okay"; + }; + + wdt@ec800620 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi new file mode 100644 index 000000000000..a26fc47a55e8 --- /dev/null +++ b/arch/arm/boot/dts/spear1340.dtsi @@ -0,0 +1,56 @@ +/* + * DTS file for all SPEAr1340 SoCs + * + * Copyright 2012 Viresh Kumar <viresh.kumar@st.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "spear13xx.dtsi" + +/ { + compatible = "st,spear1340"; + + ahb { + ahci@b1000000 { + compatible = "snps,spear-ahci"; + reg = <0xb1000000 0x10000>; + interrupts = <0 72 0x4>; + status = "disabled"; + }; + + spi1: spi@5d400000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x5d400000 0x1000>; + interrupts = <0 99 0x4>; + status = "disabled"; + }; + + apb { + i2c1: i2c@b4000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xb4000000 0x1000>; + interrupts = <0 104 0x4>; + status = "disabled"; + }; + + serial@b4100000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb4100000 0x1000>; + interrupts = <0 105 0x4>; + status = "disabled"; + }; + + thermal@e07008c4 { + st,thermal-flags = <0x2a00>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi new file mode 100644 index 000000000000..1f8e1e1481df --- /dev/null +++ b/arch/arm/boot/dts/spear13xx.dtsi @@ -0,0 +1,262 @@ +/* + * DTS file for all SPEAr13xx SoCs + * + * Copyright 2012 Viresh Kumar <viresh.kumar@st.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + + gic: interrupt-controller@ec801000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0xec801000 0x1000 >, + < 0xec800100 0x0100 >; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 8 0x04 + 0 9 0x04>; + }; + + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0xed000000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0 0x40000000>; + }; + + chosen { + bootargs = "console=ttyAMA0,115200"; + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x50000000 0x50000000 0x10000000 + 0xb0000000 0xb0000000 0x10000000 + 0xe0000000 0xe0000000 0x10000000>; + + sdhci@b3000000 { + compatible = "st,sdhci-spear"; + reg = <0xb3000000 0x100>; + interrupts = <0 28 0x4>; + status = "disabled"; + }; + + cf@b2800000 { + compatible = "arasan,cf-spear1340"; + reg = <0xb2800000 0x100>; + interrupts = <0 29 0x4>; + status = "disabled"; + }; + + dma@ea800000 { + compatible = "snps,dma-spear1340"; + reg = <0xea800000 0x1000>; + interrupts = <0 19 0x4>; + status = "disabled"; + }; + + dma@eb000000 { + compatible = "snps,dma-spear1340"; + reg = <0xeb000000 0x1000>; + interrupts = <0 59 0x4>; + status = "disabled"; + }; + + fsmc: flash@b0000000 { + compatible = "st,spear600-fsmc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb0000000 0x1000 /* FSMC Register */ + 0xb0800000 0x0010>; /* NAND Base */ + reg-names = "fsmc_regs", "nand_data"; + interrupts = <0 20 0x4 + 0 21 0x4 + 0 22 0x4 + 0 23 0x4>; + st,ale-off = <0x20000>; + st,cle-off = <0x10000>; + status = "disabled"; + }; + + gmac0: eth@e2000000 { + compatible = "st,spear600-gmac"; + reg = <0xe2000000 0x8000>; + interrupts = <0 23 0x4 + 0 24 0x4>; + interrupt-names = "macirq", "eth_wake_irq"; + status = "disabled"; + }; + + smi: flash@ea000000 { + compatible = "st,spear600-smi"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xea000000 0x1000>; + interrupts = <0 30 0x4>; + status = "disabled"; + }; + + spi0: spi@e0100000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xe0100000 0x1000>; + interrupts = <0 31 0x4>; + status = "disabled"; + }; + + ehci@e4800000 { + compatible = "st,spear600-ehci", "usb-ehci"; + reg = <0xe4800000 0x1000>; + interrupts = <0 64 0x4>; + status = "disabled"; + }; + + ehci@e5800000 { + compatible = "st,spear600-ehci", "usb-ehci"; + reg = <0xe5800000 0x1000>; + interrupts = <0 66 0x4>; + status = "disabled"; + }; + + ohci@e4000000 { + compatible = "st,spear600-ohci", "usb-ohci"; + reg = <0xe4000000 0x1000>; + interrupts = <0 65 0x4>; + status = "disabled"; + }; + + ohci@e5000000 { + compatible = "st,spear600-ohci", "usb-ohci"; + reg = <0xe5000000 0x1000>; + interrupts = <0 67 0x4>; + status = "disabled"; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x50000000 0x50000000 0x10000000 + 0xb0000000 0xb0000000 0x10000000 + 0xe0000000 0xe0000000 0x10000000>; + + gpio0: gpio@e0600000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xe0600000 0x1000>; + interrupts = <0 24 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio1: gpio@e0680000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xe0680000 0x1000>; + interrupts = <0 25 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + kbd@e0300000 { + compatible = "st,spear300-kbd"; + reg = <0xe0300000 0x1000>; + status = "disabled"; + }; + + i2c0: i2c@e0280000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xe0280000 0x1000>; + interrupts = <0 41 0x4>; + status = "disabled"; + }; + + rtc@e0580000 { + compatible = "st,spear-rtc"; + reg = <0xe0580000 0x1000>; + interrupts = <0 36 0x4>; + status = "disabled"; + }; + + serial@e0000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xe0000000 0x1000>; + interrupts = <0 36 0x4>; + status = "disabled"; + }; + + adc@e0080000 { + compatible = "st,spear600-adc"; + reg = <0xe0080000 0x1000>; + interrupts = <0 44 0x4>; + status = "disabled"; + }; + + timer@e0380000 { + compatible = "st,spear-timer"; + reg = <0xe0380000 0x400>; + interrupts = <0 37 0x4>; + }; + + timer@ec800600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xec800600 0x20>; + interrupts = <1 13 0x301>; + }; + + wdt@ec800620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0xec800620 0x20>; + status = "disabled"; + }; + + thermal@e07008c4 { + compatible = "st,thermal-spear1340"; + reg = <0xe07008c4 0x4>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts new file mode 100644 index 000000000000..fc82b1a26458 --- /dev/null +++ b/arch/arm/boot/dts/spear300-evb.dts @@ -0,0 +1,246 @@ +/* + * DTS file for SPEAr300 Evaluation Baord + * + * Copyright 2012 Viresh Kumar <viresh.kumar@st.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "spear300.dtsi" + +/ { + model = "ST SPEAr300 Evaluation Board"; + compatible = "st,spear300-evb", "st,spear300"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + reg = <0 0x40000000>; + }; + + ahb { + pinmux@99000000 { + st,pinmux-mode = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + i2c0 { + st,pins = "i2c0_grp"; + st,function = "i2c0"; + }; + ssp0 { + st,pins = "ssp0_grp"; + st,function = "ssp0"; + }; + mii0 { + st,pins = "mii0_grp"; + st,function = "mii0"; + }; + uart0 { + st,pins = "uart0_grp"; + st,function = "uart0"; + }; + clcd { + st,pins = "clcd_pfmode_grp"; + st,function = "clcd"; + }; + sdhci { + st,pins = "sdhci_4bit_grp"; + st,function = "sdhci"; + }; + gpio1 { + st,pins = "gpio1_4_to_7_grp", + "gpio1_0_to_3_grp"; + st,function = "gpio1"; + }; + }; + }; + + clcd@60000000 { + status = "okay"; + }; + + dma@fc400000 { + status = "okay"; + }; + + fsmc: flash@94000000 { + status = "okay"; + }; + + gmac: eth@e0800000 { + status = "okay"; + }; + + sdhci@70000000 { + int-gpio = <&gpio1 0 0>; + power-gpio = <&gpio1 2 1>; + status = "okay"; + }; + + smi: flash@fc000000 { + status = "okay"; + clock-rate=<50000000>; + + flash@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf8000000 0x800000>; + st,smi-fast-mode; + + partition@0 { + label = "xloader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "u-boot"; + reg = <0x10000 0x40000>; + }; + partition@50000 { + label = "linux"; + reg = <0x50000 0x2c0000>; + }; + partition@310000 { + label = "rootfs"; + reg = <0x310000 0x4f0000>; + }; + }; + }; + + spi0: spi@d0100000 { + status = "okay"; + }; + + ehci@e1800000 { + status = "okay"; + }; + + ohci@e1900000 { + status = "okay"; + }; + + ohci@e2100000 { + status = "okay"; + }; + + apb { + gpio0: gpio@fc980000 { + status = "okay"; + }; + + gpio1: gpio@a9000000 { + status = "okay"; + }; + + i2c0: i2c@d0180000 { + status = "okay"; + }; + + kbd@a0000000 { + linux,keymap = < 0x00000001 + 0x00010002 + 0x00020003 + 0x00030004 + 0x00040005 + 0x00050006 + 0x00060007 + 0x00070008 + 0x00080009 + 0x0100000a + 0x0101000c + 0x0102000d + 0x0103000e + 0x0104000f + 0x01050010 + 0x01060011 + 0x01070012 + 0x01080013 + 0x02000014 + 0x02010015 + 0x02020016 + 0x02030017 + 0x02040018 + 0x02050019 + 0x0206001a + 0x0207001b + 0x0208001c + 0x0300001d + 0x0301001e + 0x0302001f + 0x03030020 + 0x03040021 + 0x03050022 + 0x03060023 + 0x03070024 + 0x03080025 + 0x04000026 + 0x04010027 + 0x04020028 + 0x04030029 + 0x0404002a + 0x0405002b + 0x0406002c + 0x0407002d + 0x0408002e + 0x0500002f + 0x05010030 + 0x05020031 + 0x05030032 + 0x05040033 + 0x05050034 + 0x05060035 + 0x05070036 + 0x05080037 + 0x06000038 + 0x06010039 + 0x0602003a + 0x0603003b + 0x0604003c + 0x0605003d + 0x0606003e + 0x0607003f + 0x06080040 + 0x07000041 + 0x07010042 + 0x07020043 + 0x07030044 + 0x07040045 + 0x07050046 + 0x07060047 + 0x07070048 + 0x07080049 + 0x0800004a + 0x0801004b + 0x0802004c + 0x0803004d + 0x0804004e + 0x0805004f + 0x08060050 + 0x08070051 + 0x08080052 >; + autorepeat; + st,mode = <0>; + status = "okay"; + }; + + rtc@fc900000 { + status = "okay"; + }; + + serial@d0000000 { + status = "okay"; + }; + + wdt@fc880000 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi new file mode 100644 index 000000000000..01c5e358fdb2 --- /dev/null +++ b/arch/arm/boot/dts/spear300.dtsi @@ -0,0 +1,77 @@ +/* + * DTS file for SPEAr300 SoC + * + * Copyright 2012 Viresh Kumar <viresh.kumar@st.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "spear3xx.dtsi" + +/ { + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x60000000 0x60000000 0x50000000 + 0xd0000000 0xd0000000 0x30000000>; + + pinmux@99000000 { + compatible = "st,spear300-pinmux"; + reg = <0x99000000 0x1000>; + }; + + clcd@60000000 { + compatible = "arm,clcd-pl110", "arm,primecell"; + reg = <0x60000000 0x1000>; + interrupts = <30>; + status = "disabled"; + }; + + fsmc: flash@94000000 { + compatible = "st,spear600-fsmc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x94000000 0x1000 /* FSMC Register */ + 0x80000000 0x0010>; /* NAND Base */ + reg-names = "fsmc_regs", "nand_data"; + st,ale-off = <0x20000>; + st,cle-off = <0x10000>; + status = "disabled"; + }; + + sdhci@70000000 { + compatible = "st,sdhci-spear"; + reg = <0x70000000 0x100>; + interrupts = <1>; + status = "disabled"; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0xa0000000 0xa0000000 0x10000000 + 0xd0000000 0xd0000000 0x30000000>; + + gpio1: gpio@a9000000 { + #gpio-cells = <2>; + compatible = "arm,pl061", "arm,primecell"; + gpio-controller; + reg = <0xa9000000 0x1000>; + status = "disabled"; + }; + + kbd@a0000000 { + compatible = "st,spear300-kbd"; + reg = <0xa0000000 0x1000>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts new file mode 100644 index 000000000000..dc5e2d445a93 --- /dev/null +++ b/arch/arm/boot/dts/spear310-evb.dts @@ -0,0 +1,188 @@ +/* + * DTS file for SPEAr310 Evaluation Baord + * + * Copyright 2012 Viresh Kumar <viresh.kumar@st.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "spear310.dtsi" + +/ { + model = "ST SPEAr310 Evaluation Board"; + compatible = "st,spear310-evb", "st,spear310"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + reg = <0 0x40000000>; + }; + + ahb { + pinmux@b4000000 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + gpio0 { + st,pins = "gpio0_pin0_grp", + "gpio0_pin1_grp", + "gpio0_pin2_grp", + "gpio0_pin3_grp", + "gpio0_pin4_grp", + "gpio0_pin5_grp"; + st,function = "gpio0"; + }; + i2c0 { + st,pins = "i2c0_grp"; + st,function = "i2c0"; + }; + mii0 { + st,pins = "mii0_grp"; + st,function = "mii0"; + }; + ssp0 { + st,pins = "ssp0_grp"; + st,function = "ssp0"; + }; + uart0 { + st,pins = "uart0_grp"; + st,function = "uart0"; + }; + emi { + st,pins = "emi_cs_0_to_5_grp"; + st,function = "emi"; + }; + fsmc { + st,pins = "fsmc_grp"; + st,function = "fsmc"; + }; + uart1 { + st,pins = "uart1_grp"; + st,function = "uart1"; + }; + uart2 { + st,pins = "uart2_grp"; + st,function = "uart2"; + }; + uart3 { + st,pins = "uart3_grp"; + st,function = "uart3"; + }; + uart4 { + st,pins = "uart4_grp"; + st,function = "uart4"; + }; + uart5 { + st,pins = "uart5_grp"; + st,function = "uart5"; + }; + }; + }; + + dma@fc400000 { + status = "okay"; + }; + + fsmc: flash@44000000 { + status = "okay"; + }; + + gmac: eth@e0800000 { + status = "okay"; + }; + + smi: flash@fc000000 { + status = "okay"; + clock-rate=<50000000>; + + flash@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf8000000 0x800000>; + st,smi-fast-mode; + + partition@0 { + label = "xloader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "u-boot"; + reg = <0x10000 0x40000>; + }; + partition@50000 { + label = "linux"; + reg = <0x50000 0x2c0000>; + }; + partition@310000 { + label = "rootfs"; + reg = <0x310000 0x4f0000>; + }; + }; + }; + + spi0: spi@d0100000 { + status = "okay"; + }; + + ehci@e1800000 { + status = "okay"; + }; + + ohci@e1900000 { + status = "okay"; + }; + + ohci@e2100000 { + status = "okay"; + }; + + apb { + gpio0: gpio@fc980000 { + status = "okay"; + }; + + i2c0: i2c@d0180000 { + status = "okay"; + }; + + rtc@fc900000 { + status = "okay"; + }; + + serial@d0000000 { + status = "okay"; + }; + + serial@b2000000 { + status = "okay"; + }; + + serial@b2080000 { + status = "okay"; + }; + + serial@b2100000 { + status = "okay"; + }; + + serial@b2180000 { + status = "okay"; + }; + + serial@b2200000 { + status = "okay"; + }; + + wdt@fc880000 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi new file mode 100644 index 000000000000..e47081c494d9 --- /dev/null +++ b/arch/arm/boot/dts/spear310.dtsi @@ -0,0 +1,80 @@ +/* + * DTS file for SPEAr310 SoC + * + * Copyright 2012 Viresh Kumar <viresh.kumar@st.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "spear3xx.dtsi" + +/ { + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x40000000 0x40000000 0x10000000 + 0xb0000000 0xb0000000 0x10000000 + 0xd0000000 0xd0000000 0x30000000>; + + pinmux@b4000000 { + compatible = "st,spear310-pinmux"; + reg = <0xb4000000 0x1000>; + }; + + fsmc: flash@44000000 { + compatible = "st,spear600-fsmc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x44000000 0x1000 /* FSMC Register */ + 0x40000000 0x0010>; /* NAND Base */ + reg-names = "fsmc_regs", "nand_data"; + st,ale-off = <0x10000>; + st,cle-off = <0x20000>; + status = "disabled"; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0xb0000000 0xb0000000 0x10000000 + 0xd0000000 0xd0000000 0x30000000>; + + serial@b2000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb2000000 0x1000>; + status = "disabled"; + }; + + serial@b2080000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb2080000 0x1000>; + status = "disabled"; + }; + + serial@b2100000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb2100000 0x1000>; + status = "disabled"; + }; + + serial@b2180000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb2180000 0x1000>; + status = "disabled"; + }; + + serial@b2200000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xb2200000 0x1000>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts new file mode 100644 index 000000000000..6308fa3bec1e --- /dev/null +++ b/arch/arm/boot/dts/spear320-evb.dts @@ -0,0 +1,198 @@ +/* + * DTS file for SPEAr320 Evaluation Baord + * + * Copyright 2012 Viresh Kumar <viresh.kumar@st.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "spear320.dtsi" + +/ { + model = "ST SPEAr300 Evaluation Board"; + compatible = "st,spear300-evb", "st,spear300"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + reg = <0 0x40000000>; + }; + + ahb { + pinmux@b3000000 { + st,pinmux-mode = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + i2c0 { + st,pins = "i2c0_grp"; + st,function = "i2c0"; + }; + mii0 { + st,pins = "mii0_grp"; + st,function = "mii0"; + }; + ssp0 { + st,pins = "ssp0_grp"; + st,function = "ssp0"; + }; + uart0 { + st,pins = "uart0_grp"; + st,function = "uart0"; + }; + sdhci { + st,pins = "sdhci_cd_51_grp"; + st,function = "sdhci"; + }; + i2s { + st,pins = "i2s_grp"; + st,function = "i2s"; + }; + uart1 { + st,pins = "uart1_grp"; + st,function = "uart1"; + }; + uart2 { + st,pins = "uart2_grp"; + st,function = "uart2"; + }; + can0 { + st,pins = "can0_grp"; + st,function = "can0"; + }; + can1 { + st,pins = "can1_grp"; + st,function = "can1"; + }; + mii2 { + st,pins = "mii2_grp"; + st,function = "mii2"; + }; + pwm0_1 { + st,pins = "pwm0_1_pin_14_15_grp"; + st,function = "pwm0_1"; + }; + pwm2 { + st,pins = "pwm2_pin_13_grp"; + st,function = "pwm2"; + }; + }; + }; + + clcd@90000000 { + status = "okay"; + }; + + dma@fc400000 { + status = "okay"; + }; + + fsmc: flash@4c000000 { + status = "okay"; + }; + + gmac: eth@e0800000 { + status = "okay"; + }; + + sdhci@70000000 { + power-gpio = <&gpio0 2 1>; + power_always_enb; + status = "okay"; + }; + + smi: flash@fc000000 { + status = "okay"; + clock-rate=<50000000>; + + flash@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf8000000 0x800000>; + st,smi-fast-mode; + + partition@0 { + label = "xloader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "u-boot"; + reg = <0x10000 0x40000>; + }; + partition@50000 { + label = "linux"; + reg = <0x50000 0x2c0000>; + }; + partition@310000 { + label = "rootfs"; + reg = <0x310000 0x4f0000>; + }; + }; + }; + + spi0: spi@d0100000 { + status = "okay"; + }; + + spi1: spi@a5000000 { + status = "okay"; + }; + + spi2: spi@a6000000 { + status = "okay"; + }; + + ehci@e1800000 { + status = "okay"; + }; + + ohci@e1900000 { + status = "okay"; + }; + + ohci@e2100000 { + status = "okay"; + }; + + apb { + gpio0: gpio@fc980000 { + status = "okay"; + }; + + i2c0: i2c@d0180000 { + status = "okay"; + }; + + i2c1: i2c@a7000000 { + status = "okay"; + }; + + rtc@fc900000 { + status = "okay"; + }; + + serial@d0000000 { + status = "okay"; + }; + + serial@a3000000 { + status = "okay"; + }; + + serial@a4000000 { + status = "okay"; + }; + + wdt@fc880000 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi new file mode 100644 index 000000000000..5372ca399b1f --- /dev/null +++ b/arch/arm/boot/dts/spear320.dtsi @@ -0,0 +1,95 @@ +/* + * DTS file for SPEAr320 SoC + * + * Copyright 2012 Viresh Kumar <viresh.kumar@st.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "spear3xx.dtsi" + +/ { + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x40000000 0x40000000 0x80000000 + 0xd0000000 0xd0000000 0x30000000>; + + pinmux@b3000000 { + compatible = "st,spear320-pinmux"; + reg = <0xb3000000 0x1000>; + }; + + clcd@90000000 { + compatible = "arm,clcd-pl110", "arm,primecell"; + reg = <0x90000000 0x1000>; + interrupts = <33>; + status = "disabled"; + }; + + fsmc: flash@4c000000 { + compatible = "st,spear600-fsmc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x4c000000 0x1000 /* FSMC Register */ + 0x50000000 0x0010>; /* NAND Base */ + reg-names = "fsmc_regs", "nand_data"; + st,ale-off = <0x20000>; + st,cle-off = <0x10000>; + status = "disabled"; + }; + + sdhci@70000000 { + compatible = "st,sdhci-spear"; + reg = <0x70000000 0x100>; + interrupts = <29>; + status = "disabled"; + }; + + spi1: spi@a5000000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xa5000000 0x1000>; + status = "disabled"; + }; + + spi2: spi@a6000000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xa6000000 0x1000>; + status = "disabled"; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0xa0000000 0xa0000000 0x10000000 + 0xd0000000 0xd0000000 0x30000000>; + + i2c1: i2c@a7000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xa7000000 0x1000>; + status = "disabled"; + }; + + serial@a3000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xa3000000 0x1000>; + status = "disabled"; + }; + + serial@a4000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xa4000000 0x1000>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi new file mode 100644 index 000000000000..91072553963f --- /dev/null +++ b/arch/arm/boot/dts/spear3xx.dtsi @@ -0,0 +1,150 @@ +/* + * DTS file for all SPEAr3xx SoCs + * + * Copyright 2012 Viresh Kumar <viresh.kumar@st.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + interrupt-parent = <&vic>; + + cpus { + cpu@0 { + compatible = "arm,arm926ejs"; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0xd0000000 0xd0000000 0x30000000>; + + vic: interrupt-controller@f1100000 { + compatible = "arm,pl190-vic"; + interrupt-controller; + reg = <0xf1100000 0x1000>; + #interrupt-cells = <1>; + }; + + dma@fc400000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0xfc400000 0x1000>; + interrupt-parent = <&vic>; + interrupts = <8>; + status = "disabled"; + }; + + gmac: eth@e0800000 { + compatible = "st,spear600-gmac"; + reg = <0xe0800000 0x8000>; + interrupts = <23 22>; + interrupt-names = "macirq", "eth_wake_irq"; + status = "disabled"; + }; + + smi: flash@fc000000 { + compatible = "st,spear600-smi"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xfc000000 0x1000>; + interrupts = <9>; + status = "disabled"; + }; + + spi0: spi@d0100000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xd0100000 0x1000>; + interrupts = <20>; + status = "disabled"; + }; + + ehci@e1800000 { + compatible = "st,spear600-ehci", "usb-ehci"; + reg = <0xe1800000 0x1000>; + interrupts = <26>; + status = "disabled"; + }; + + ohci@e1900000 { + compatible = "st,spear600-ohci", "usb-ohci"; + reg = <0xe1900000 0x1000>; + interrupts = <25>; + status = "disabled"; + }; + + ohci@e2100000 { + compatible = "st,spear600-ohci", "usb-ohci"; + reg = <0xe2100000 0x1000>; + interrupts = <27>; + status = "disabled"; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0xd0000000 0xd0000000 0x30000000>; + + gpio0: gpio@fc980000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xfc980000 0x1000>; + interrupts = <11>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + i2c0: i2c@d0180000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xd0180000 0x1000>; + interrupts = <21>; + status = "disabled"; + }; + + rtc@fc900000 { + compatible = "st,spear-rtc"; + reg = <0xfc900000 0x1000>; + interrupts = <10>; + status = "disabled"; + }; + + serial@d0000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xd0000000 0x1000>; + interrupts = <19>; + status = "disabled"; + }; + + wdt@fc880000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0xfc880000 0x1000>; + interrupts = <12>; + status = "disabled"; + }; + + timer@f0000000 { + compatible = "st,spear-timer"; + reg = <0xf0000000 0x400>; + interrupts = <2>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts index 636292e18c90..1119c22c9a82 100644 --- a/arch/arm/boot/dts/spear600-evb.dts +++ b/arch/arm/boot/dts/spear600-evb.dts @@ -24,11 +24,44 @@ }; ahb { + dma@fc400000 { + status = "okay"; + }; + gmac: ethernet@e0800000 { phy-mode = "gmii"; status = "okay"; }; + smi: flash@fc000000 { + status = "okay"; + clock-rate=<50000000>; + + flash@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf8000000 0x800000>; + st,smi-fast-mode; + + partition@0 { + label = "xloader"; + reg = <0x0 0x10000>; + }; + partition@10000 { + label = "u-boot"; + reg = <0x10000 0x40000>; + }; + partition@50000 { + label = "linux"; + reg = <0x50000 0x2c0000>; + }; + partition@310000 { + label = "rootfs"; + reg = <0x310000 0x4f0000>; + }; + }; + }; + apb { serial@d0000000 { status = "okay"; diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi index ebe0885a2b98..089f0a42c50e 100644 --- a/arch/arm/boot/dts/spear600.dtsi +++ b/arch/arm/boot/dts/spear600.dtsi @@ -45,6 +45,14 @@ #interrupt-cells = <1>; }; + dma@fc400000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0xfc400000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <10>; + status = "disabled"; + }; + gmac: ethernet@e0800000 { compatible = "st,spear600-gmac"; reg = <0xe0800000 0x8000>; @@ -169,6 +177,12 @@ interrupts = <28>; status = "disabled"; }; + + timer@f0000000 { + compatible = "st,spear-timer"; + reg = <0xf0000000 0x400>; + interrupts = <16>; + }; }; }; }; diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig new file mode 100644 index 000000000000..1fdb82694ca2 --- /dev/null +++ b/arch/arm/configs/spear13xx_defconfig @@ -0,0 +1,95 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_PLAT_SPEAR=y +CONFIG_ARCH_SPEAR13XX=y +CONFIG_MACH_SPEAR1310=y +CONFIG_MACH_SPEAR1340=y +# CONFIG_SWP_EMULATE is not set +CONFIG_SMP=y +# CONFIG_SMP_ON_UP is not set +# CONFIG_ARM_CPU_TOPOLOGY is not set +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_BINFMT_MISC=y +CONFIG_NET=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_OF_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_FSMC=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_ATA=y +# CONFIG_SATA_PMP is not set +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_PATA_ARASAN_CF=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +CONFIG_STMMAC_ETH=y +# CONFIG_WLAN is not set +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_SPEAR=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +# CONFIG_HW_RANDOM is not set +CONFIG_RAW_DRIVER=y +CONFIG_MAX_RAW_DEVS=8192 +CONFIG_I2C=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_SPI=y +CONFIG_SPI_PL022=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_PL061=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_MPCORE_WATCHDOG=y +# CONFIG_HID_SUPPORT is not set +CONFIG_USB=y +# CONFIG_USB_DEVICE_CLASS is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SPEAR=y +CONFIG_RTC_CLASS=y +CONFIG_DMADEVICES=y +CONFIG_DW_DMAC=y +CONFIG_DMATEST=m +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_AUTOFS4_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=m +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_INFO=y diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig index fea7e1f026a3..865980c5f212 100644 --- a/arch/arm/configs/spear3xx_defconfig +++ b/arch/arm/configs/spear3xx_defconfig @@ -2,33 +2,70 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y +CONFIG_PARTITION_ADVANCED=y CONFIG_PLAT_SPEAR=y -CONFIG_BOARD_SPEAR300_EVB=y -CONFIG_BOARD_SPEAR310_EVB=y -CONFIG_BOARD_SPEAR320_EVB=y +CONFIG_MACH_SPEAR300=y +CONFIG_MACH_SPEAR310=y +CONFIG_MACH_SPEAR320=y CONFIG_BINFMT_MISC=y +CONFIG_NET=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_OF_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_FSMC=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +CONFIG_STMMAC_ETH=y +# CONFIG_WLAN is not set CONFIG_INPUT_FF_MEMLESS=y # CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_SPEAR=y # CONFIG_INPUT_MOUSE is not set +# CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set # CONFIG_HW_RANDOM is not set CONFIG_RAW_DRIVER=y CONFIG_MAX_RAW_DEVS=8192 +CONFIG_I2C=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_SPI=y +CONFIG_SPI_PL022=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PL061=y # CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_ARM_SP805_WATCHDOG=y +CONFIG_FB=y +CONFIG_FB_ARMCLCD=y # CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set +CONFIG_USB=y +# CONFIG_USB_DEVICE_CLASS is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SPEAR=y +CONFIG_RTC_CLASS=y +CONFIG_DMADEVICES=y +CONFIG_AMBA_PL08X=y +CONFIG_DMATEST=m CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_SECURITY=y @@ -39,8 +76,7 @@ CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_IOCHARSET="ascii" CONFIG_TMPFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS=y +CONFIG_JFFS2_FS=y CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=m @@ -48,6 +84,4 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_SPINLOCK_SLEEP=y CONFIG_DEBUG_INFO=y -# CONFIG_CRC32 is not set diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig index cef2e836afd2..a2a1265f86b6 100644 --- a/arch/arm/configs/spear6xx_defconfig +++ b/arch/arm/configs/spear6xx_defconfig @@ -2,29 +2,60 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y +CONFIG_PARTITION_ADVANCED=y CONFIG_PLAT_SPEAR=y CONFIG_ARCH_SPEAR6XX=y -CONFIG_BOARD_SPEAR600_EVB=y CONFIG_BINFMT_MISC=y +CONFIG_NET=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_OF_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_FSMC=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +CONFIG_STMMAC_ETH=y +# CONFIG_WLAN is not set CONFIG_INPUT_FF_MEMLESS=y # CONFIG_INPUT_MOUSEDEV_PSAUX is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set CONFIG_RAW_DRIVER=y CONFIG_MAX_RAW_DEVS=8192 +CONFIG_I2C=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_SPI=y +CONFIG_SPI_PL022=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PL061=y # CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_ARM_SP805_WATCHDOG=y # CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_RTC_CLASS=y +CONFIG_DMADEVICES=y +CONFIG_AMBA_PL08X=y +CONFIG_DMATEST=m CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_SECURITY=y @@ -35,8 +66,7 @@ CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_IOCHARSET="ascii" CONFIG_TMPFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS=y +CONFIG_JFFS2_FS=y CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=m @@ -44,6 +74,4 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_SPINLOCK_SLEEP=y CONFIG_DEBUG_INFO=y -# CONFIG_CRC32 is not set diff --git a/arch/arm/mach-spear13xx/Kconfig b/arch/arm/mach-spear13xx/Kconfig new file mode 100644 index 000000000000..eaadc66d96b3 --- /dev/null +++ b/arch/arm/mach-spear13xx/Kconfig @@ -0,0 +1,20 @@ +# +# SPEAr13XX Machine configuration file +# + +if ARCH_SPEAR13XX + +menu "SPEAr13xx Implementations" +config MACH_SPEAR1310 + bool "SPEAr1310 Machine support with Device Tree" + select PINCTRL_SPEAR1310 + help + Supports ST SPEAr1310 machine configured via the device-tree + +config MACH_SPEAR1340 + bool "SPEAr1340 Machine support with Device Tree" + select PINCTRL_SPEAR1340 + help + Supports ST SPEAr1340 machine configured via the device-tree +endmenu +endif #ARCH_SPEAR13XX diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile new file mode 100644 index 000000000000..3435ea78c15d --- /dev/null +++ b/arch/arm/mach-spear13xx/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for SPEAr13XX machine series +# + +obj-$(CONFIG_SMP) += headsmp.o platsmp.o +obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o + +obj-$(CONFIG_ARCH_SPEAR13XX) += spear13xx.o +obj-$(CONFIG_MACH_SPEAR1310) += spear1310.o +obj-$(CONFIG_MACH_SPEAR1340) += spear1340.o diff --git a/arch/arm/mach-spear13xx/Makefile.boot b/arch/arm/mach-spear13xx/Makefile.boot new file mode 100644 index 000000000000..403efd7e6d27 --- /dev/null +++ b/arch/arm/mach-spear13xx/Makefile.boot @@ -0,0 +1,6 @@ +zreladdr-y += 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 + +dtb-$(CONFIG_MACH_SPEAR1310) += spear1310-evb.dtb +dtb-$(CONFIG_MACH_SPEAR1340) += spear1340-evb.dtb diff --git a/arch/arm/mach-spear13xx/headsmp.S b/arch/arm/mach-spear13xx/headsmp.S new file mode 100644 index 000000000000..ed85473a047f --- /dev/null +++ b/arch/arm/mach-spear13xx/headsmp.S @@ -0,0 +1,47 @@ +/* + * arch/arm/mach-spear13XX/headsmp.S + * + * Picked from realview + * Copyright (c) 2012 ST Microelectronics Limited + * Shiraz Hashim <shiraz.hashim@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/linkage.h> +#include <linux/init.h> + + __INIT + +/* + * spear13xx specific entry point for secondary CPUs. This provides + * a "holding pen" into which all secondary cores are held until we're + * ready for them to initialise. + */ +ENTRY(spear13xx_secondary_startup) + mrc p15, 0, r0, c0, c0, 5 + and r0, r0, #15 + adr r4, 1f + ldmia r4, {r5, r6} + sub r4, r4, r5 + add r6, r6, r4 +pen: ldr r7, [r6] + cmp r7, r0 + bne pen + + /* re-enable coherency */ + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #(1 << 6) | (1 << 0) + mcr p15, 0, r0, c1, c0, 1 + /* + * we've been released from the holding pen: secondary_stack + * should now contain the SVC stack for this core + */ + b secondary_startup + + .align +1: .long . + .long pen_release +ENDPROC(spear13xx_secondary_startup) diff --git a/arch/arm/mach-spear13xx/hotplug.c b/arch/arm/mach-spear13xx/hotplug.c new file mode 100644 index 000000000000..5c6867b46d09 --- /dev/null +++ b/arch/arm/mach-spear13xx/hotplug.c @@ -0,0 +1,119 @@ +/* + * linux/arch/arm/mach-spear13xx/hotplug.c + * + * Copyright (C) 2012 ST Microelectronics Ltd. + * Deepak Sikri <deepak.sikri@st.com> + * + * based upon linux/arch/arm/mach-realview/hotplug.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/smp.h> +#include <asm/cacheflush.h> +#include <asm/cp15.h> +#include <asm/smp_plat.h> + +extern volatile int pen_release; + +static inline void cpu_enter_lowpower(void) +{ + unsigned int v; + + flush_cache_all(); + asm volatile( + " mcr p15, 0, %1, c7, c5, 0\n" + " dsb\n" + /* + * Turn off coherency + */ + " mrc p15, 0, %0, c1, c0, 1\n" + " bic %0, %0, #0x20\n" + " mcr p15, 0, %0, c1, c0, 1\n" + " mrc p15, 0, %0, c1, c0, 0\n" + " bic %0, %0, %2\n" + " mcr p15, 0, %0, c1, c0, 0\n" + : "=&r" (v) + : "r" (0), "Ir" (CR_C) + : "cc", "memory"); +} + +static inline void cpu_leave_lowpower(void) +{ + unsigned int v; + + asm volatile("mrc p15, 0, %0, c1, c0, 0\n" + " orr %0, %0, %1\n" + " mcr p15, 0, %0, c1, c0, 0\n" + " mrc p15, 0, %0, c1, c0, 1\n" + " orr %0, %0, #0x20\n" + " mcr p15, 0, %0, c1, c0, 1\n" + : "=&r" (v) + : "Ir" (CR_C) + : "cc"); +} + +static inline void platform_do_lowpower(unsigned int cpu, int *spurious) +{ + for (;;) { + wfi(); + + if (pen_release == cpu) { + /* + * OK, proper wakeup, we're done + */ + break; + } + + /* + * Getting here, means that we have come out of WFI without + * having been woken up - this shouldn't happen + * + * Just note it happening - when we're woken, we can report + * its occurrence. + */ + (*spurious)++; + } +} + +int platform_cpu_kill(unsigned int cpu) +{ + return 1; +} + +/* + * platform-specific code to shutdown a CPU + * + * Called with IRQs disabled + */ +void __cpuinit platform_cpu_die(unsigned int cpu) +{ + int spurious = 0; + + /* + * we're ready for shutdown now, so do it + */ + cpu_enter_lowpower(); + platform_do_lowpower(cpu, &spurious); + + /* + * bring this CPU back into the world of cache + * coherency, and then restore interrupts + */ + cpu_leave_lowpower(); + + if (spurious) + pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); +} + +int platform_cpu_disable(unsigned int cpu) +{ + /* + * we don't allow CPU 0 to be shutdown (it is still too special + * e.g. clock tick interrupts) + */ + return cpu == 0 ? -EPERM : 0; +} diff --git a/arch/arm/mach-spear13xx/include/mach/debug-macro.S b/arch/arm/mach-spear13xx/include/mach/debug-macro.S new file mode 100644 index 000000000000..ea1564609bd4 --- /dev/null +++ b/arch/arm/mach-spear13xx/include/mach/debug-macro.S @@ -0,0 +1,14 @@ +/* + * arch/arm/mach-spear13xx/include/mach/debug-macro.S + * + * Debugging macro include header spear13xx machine family + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <plat/debug-macro.S> diff --git a/arch/arm/mach-spear13xx/include/mach/dma.h b/arch/arm/mach-spear13xx/include/mach/dma.h new file mode 100644 index 000000000000..383ab04dc6c9 --- /dev/null +++ b/arch/arm/mach-spear13xx/include/mach/dma.h @@ -0,0 +1,128 @@ +/* + * arch/arm/mach-spear13xx/include/mach/dma.h + * + * DMA information for SPEAr13xx machine family + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_DMA_H +#define __MACH_DMA_H + +/* request id of all the peripherals */ +enum dma_master_info { + /* Accessible from only one master */ + DMA_MASTER_MCIF = 0, + DMA_MASTER_FSMC = 1, + /* Accessible from both 0 & 1 */ + DMA_MASTER_MEMORY = 0, + DMA_MASTER_ADC = 0, + DMA_MASTER_UART0 = 0, + DMA_MASTER_SSP0 = 0, + DMA_MASTER_I2C0 = 0, + +#ifdef CONFIG_MACH_SPEAR1310 + /* Accessible from only one master */ + SPEAR1310_DMA_MASTER_JPEG = 1, + + /* Accessible from both 0 & 1 */ + SPEAR1310_DMA_MASTER_I2S = 0, + SPEAR1310_DMA_MASTER_UART1 = 0, + SPEAR1310_DMA_MASTER_UART2 = 0, + SPEAR1310_DMA_MASTER_UART3 = 0, + SPEAR1310_DMA_MASTER_UART4 = 0, + SPEAR1310_DMA_MASTER_UART5 = 0, + SPEAR1310_DMA_MASTER_I2C1 = 0, + SPEAR1310_DMA_MASTER_I2C2 = 0, + SPEAR1310_DMA_MASTER_I2C3 = 0, + SPEAR1310_DMA_MASTER_I2C4 = 0, + SPEAR1310_DMA_MASTER_I2C5 = 0, + SPEAR1310_DMA_MASTER_I2C6 = 0, + SPEAR1310_DMA_MASTER_I2C7 = 0, + SPEAR1310_DMA_MASTER_SSP1 = 0, +#endif + +#ifdef CONFIG_MACH_SPEAR1340 + /* Accessible from only one master */ + SPEAR1340_DMA_MASTER_I2S_PLAY = 1, + SPEAR1340_DMA_MASTER_I2S_REC = 1, + SPEAR1340_DMA_MASTER_I2C1 = 1, + SPEAR1340_DMA_MASTER_UART1 = 1, + + /* following are accessible from both master 0 & 1 */ + SPEAR1340_DMA_MASTER_SPDIF = 0, + SPEAR1340_DMA_MASTER_CAM = 1, + SPEAR1340_DMA_MASTER_VIDEO_IN = 0, + SPEAR1340_DMA_MASTER_MALI = 0, +#endif +}; + +enum request_id { + DMA_REQ_ADC = 0, + DMA_REQ_SSP0_TX = 4, + DMA_REQ_SSP0_RX = 5, + DMA_REQ_UART0_TX = 6, + DMA_REQ_UART0_RX = 7, + DMA_REQ_I2C0_TX = 8, + DMA_REQ_I2C0_RX = 9, + +#ifdef CONFIG_MACH_SPEAR1310 + SPEAR1310_DMA_REQ_FROM_JPEG = 2, + SPEAR1310_DMA_REQ_TO_JPEG = 3, + SPEAR1310_DMA_REQ_I2S_TX = 10, + SPEAR1310_DMA_REQ_I2S_RX = 11, + + SPEAR1310_DMA_REQ_I2C1_RX = 0, + SPEAR1310_DMA_REQ_I2C1_TX = 1, + SPEAR1310_DMA_REQ_I2C2_RX = 2, + SPEAR1310_DMA_REQ_I2C2_TX = 3, + SPEAR1310_DMA_REQ_I2C3_RX = 4, + SPEAR1310_DMA_REQ_I2C3_TX = 5, + SPEAR1310_DMA_REQ_I2C4_RX = 6, + SPEAR1310_DMA_REQ_I2C4_TX = 7, + SPEAR1310_DMA_REQ_I2C5_RX = 8, + SPEAR1310_DMA_REQ_I2C5_TX = 9, + SPEAR1310_DMA_REQ_I2C6_RX = 10, + SPEAR1310_DMA_REQ_I2C6_TX = 11, + SPEAR1310_DMA_REQ_UART1_RX = 12, + SPEAR1310_DMA_REQ_UART1_TX = 13, + SPEAR1310_DMA_REQ_UART2_RX = 14, + SPEAR1310_DMA_REQ_UART2_TX = 15, + SPEAR1310_DMA_REQ_UART5_RX = 16, + SPEAR1310_DMA_REQ_UART5_TX = 17, + SPEAR1310_DMA_REQ_SSP1_RX = 18, + SPEAR1310_DMA_REQ_SSP1_TX = 19, + SPEAR1310_DMA_REQ_I2C7_RX = 20, + SPEAR1310_DMA_REQ_I2C7_TX = 21, + SPEAR1310_DMA_REQ_UART3_RX = 28, + SPEAR1310_DMA_REQ_UART3_TX = 29, + SPEAR1310_DMA_REQ_UART4_RX = 30, + SPEAR1310_DMA_REQ_UART4_TX = 31, +#endif + +#ifdef CONFIG_MACH_SPEAR1340 + SPEAR1340_DMA_REQ_SPDIF_TX = 2, + SPEAR1340_DMA_REQ_SPDIF_RX = 3, + SPEAR1340_DMA_REQ_I2S_TX = 10, + SPEAR1340_DMA_REQ_I2S_RX = 11, + SPEAR1340_DMA_REQ_UART1_TX = 12, + SPEAR1340_DMA_REQ_UART1_RX = 13, + SPEAR1340_DMA_REQ_I2C1_TX = 14, + SPEAR1340_DMA_REQ_I2C1_RX = 15, + SPEAR1340_DMA_REQ_CAM0_EVEN = 0, + SPEAR1340_DMA_REQ_CAM0_ODD = 1, + SPEAR1340_DMA_REQ_CAM1_EVEN = 2, + SPEAR1340_DMA_REQ_CAM1_ODD = 3, + SPEAR1340_DMA_REQ_CAM2_EVEN = 4, + SPEAR1340_DMA_REQ_CAM2_ODD = 5, + SPEAR1340_DMA_REQ_CAM3_EVEN = 6, + SPEAR1340_DMA_REQ_CAM3_ODD = 7, +#endif +}; + +#endif /* __MACH_DMA_H */ diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear13xx/include/mach/generic.h new file mode 100644 index 000000000000..6d8c45b9f298 --- /dev/null +++ b/arch/arm/mach-spear13xx/include/mach/generic.h @@ -0,0 +1,49 @@ +/* + * arch/arm/mach-spear13xx/include/mach/generic.h + * + * spear13xx machine family generic header file + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_GENERIC_H +#define __MACH_GENERIC_H + +#include <linux/dmaengine.h> +#include <asm/mach/time.h> + +/* Add spear13xx structure declarations here */ +extern struct sys_timer spear13xx_timer; +extern struct pl022_ssp_controller pl022_plat_data; +extern struct dw_dma_platform_data dmac_plat_data; +extern struct dw_dma_slave cf_dma_priv; +extern struct dw_dma_slave nand_read_dma_priv; +extern struct dw_dma_slave nand_write_dma_priv; + +/* Add spear13xx family function declarations here */ +void __init spear_setup_of_timer(void); +void __init spear13xx_map_io(void); +void __init spear13xx_dt_init_irq(void); +void __init spear13xx_l2x0_init(void); +bool dw_dma_filter(struct dma_chan *chan, void *slave); +void spear_restart(char, const char *); +void spear13xx_secondary_startup(void); + +#ifdef CONFIG_MACH_SPEAR1310 +void __init spear1310_clk_init(void); +#else +static inline void spear1310_clk_init(void) {} +#endif + +#ifdef CONFIG_MACH_SPEAR1340 +void __init spear1340_clk_init(void); +#else +static inline void spear1340_clk_init(void) {} +#endif + +#endif /* __MACH_GENERIC_H */ diff --git a/arch/arm/mach-spear13xx/include/mach/gpio.h b/arch/arm/mach-spear13xx/include/mach/gpio.h new file mode 100644 index 000000000000..cd6f4f86a56b --- /dev/null +++ b/arch/arm/mach-spear13xx/include/mach/gpio.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-spear13xx/include/mach/gpio.h + * + * GPIO macros for SPEAr13xx machine family + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_GPIO_H +#define __MACH_GPIO_H + +#include <plat/gpio.h> + +#endif /* __MACH_GPIO_H */ diff --git a/arch/arm/mach-spear13xx/include/mach/hardware.h b/arch/arm/mach-spear13xx/include/mach/hardware.h new file mode 100644 index 000000000000..40a8c178f10d --- /dev/null +++ b/arch/arm/mach-spear13xx/include/mach/hardware.h @@ -0,0 +1 @@ +/* empty */ diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h new file mode 100644 index 000000000000..f542a24aa5f2 --- /dev/null +++ b/arch/arm/mach-spear13xx/include/mach/irqs.h @@ -0,0 +1,20 @@ +/* + * arch/arm/mach-spear13xx/include/mach/irqs.h + * + * IRQ helper macros for spear13xx machine family + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_IRQS_H +#define __MACH_IRQS_H + +#define IRQ_GIC_END 160 +#define NR_IRQS IRQ_GIC_END + +#endif /* __MACH_IRQS_H */ diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h new file mode 100644 index 000000000000..30c57ef72686 --- /dev/null +++ b/arch/arm/mach-spear13xx/include/mach/spear.h @@ -0,0 +1,62 @@ +/* + * arch/arm/mach-spear13xx/include/mach/spear.h + * + * spear13xx Machine family specific definition + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_SPEAR13XX_H +#define __MACH_SPEAR13XX_H + +#include <asm/memory.h> + +#define PERIP_GRP2_BASE UL(0xB3000000) +#define VA_PERIP_GRP2_BASE UL(0xFE000000) +#define MCIF_SDHCI_BASE UL(0xB3000000) +#define SYSRAM0_BASE UL(0xB3800000) +#define VA_SYSRAM0_BASE UL(0xFE800000) +#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600) + +#define PERIP_GRP1_BASE UL(0xE0000000) +#define VA_PERIP_GRP1_BASE UL(0xFD000000) +#define UART_BASE UL(0xE0000000) +#define VA_UART_BASE UL(0xFD000000) +#define SSP_BASE UL(0xE0100000) +#define MISC_BASE UL(0xE0700000) +#define VA_MISC_BASE IOMEM(UL(0xFD700000)) + +#define A9SM_AND_MPMC_BASE UL(0xEC000000) +#define VA_A9SM_AND_MPMC_BASE UL(0xFC000000) + +/* A9SM peripheral offsets */ +#define A9SM_PERIP_BASE UL(0xEC800000) +#define VA_A9SM_PERIP_BASE UL(0xFC800000) +#define VA_SCU_BASE (VA_A9SM_PERIP_BASE + 0x00) + +#define L2CC_BASE UL(0xED000000) +#define VA_L2CC_BASE IOMEM(UL(0xFB000000)) + +/* others */ +#define DMAC0_BASE UL(0xEA800000) +#define DMAC1_BASE UL(0xEB000000) +#define MCIF_CF_BASE UL(0xB2800000) + +/* Devices present in SPEAr1310 */ +#ifdef CONFIG_MACH_SPEAR1310 +#define SPEAR1310_RAS_GRP1_BASE UL(0xD8000000) +#define VA_SPEAR1310_RAS_GRP1_BASE UL(0xFA000000) +#define SPEAR1310_RAS_BASE UL(0xD8400000) +#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000)) +#endif /* CONFIG_MACH_SPEAR1310 */ + +/* Debug uart for linux, will be used for debug and uncompress messages */ +#define SPEAR_DBG_UART_BASE UART_BASE +#define VA_SPEAR_DBG_UART_BASE VA_UART_BASE + +#endif /* __MACH_SPEAR13XX_H */ diff --git a/arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h b/arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h new file mode 100644 index 000000000000..e69de29bb2d1 --- /dev/null +++ b/arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h diff --git a/arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h b/arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h new file mode 100644 index 000000000000..e69de29bb2d1 --- /dev/null +++ b/arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h diff --git a/arch/arm/mach-spear13xx/include/mach/timex.h b/arch/arm/mach-spear13xx/include/mach/timex.h new file mode 100644 index 000000000000..31af3e8d976e --- /dev/null +++ b/arch/arm/mach-spear13xx/include/mach/timex.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-spear3xx/include/mach/timex.h + * + * SPEAr3XX machine family specific timex definitions + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_TIMEX_H +#define __MACH_TIMEX_H + +#include <plat/timex.h> + +#endif /* __MACH_TIMEX_H */ diff --git a/arch/arm/mach-spear13xx/include/mach/uncompress.h b/arch/arm/mach-spear13xx/include/mach/uncompress.h new file mode 100644 index 000000000000..c7840896ae6e --- /dev/null +++ b/arch/arm/mach-spear13xx/include/mach/uncompress.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-spear13xx/include/mach/uncompress.h + * + * Serial port stubs for kernel decompress status messages + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_UNCOMPRESS_H +#define __MACH_UNCOMPRESS_H + +#include <plat/uncompress.h> + +#endif /* __MACH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c new file mode 100644 index 000000000000..f5d07f2663d7 --- /dev/null +++ b/arch/arm/mach-spear13xx/platsmp.c @@ -0,0 +1,127 @@ +/* + * arch/arm/mach-spear13xx/platsmp.c + * + * based upon linux/arch/arm/mach-realview/platsmp.c + * + * Copyright (C) 2012 ST Microelectronics Ltd. + * Shiraz Hashim <shiraz.hashim@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/delay.h> +#include <linux/jiffies.h> +#include <linux/io.h> +#include <linux/smp.h> +#include <asm/cacheflush.h> +#include <asm/hardware/gic.h> +#include <asm/smp_scu.h> +#include <mach/spear.h> + +/* + * control for which core is the next to come out of the secondary + * boot "holding pen" + */ +volatile int __cpuinitdata pen_release = -1; +static DEFINE_SPINLOCK(boot_lock); + +static void __iomem *scu_base = IOMEM(VA_SCU_BASE); +extern void spear13xx_secondary_startup(void); + +void __cpuinit platform_secondary_init(unsigned int cpu) +{ + /* + * if any interrupts are already enabled for the primary + * core (e.g. timer irq), then they will not have been enabled + * for us: do so + */ + gic_secondary_init(0); + + /* + * let the primary processor know we're out of the + * pen, then head off into the C entry point + */ + pen_release = -1; + smp_wmb(); + + /* + * Synchronise with the boot thread. + */ + spin_lock(&boot_lock); + spin_unlock(&boot_lock); +} + +int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + unsigned long timeout; + + /* + * set synchronisation state between this boot processor + * and the secondary one + */ + spin_lock(&boot_lock); + + /* + * The secondary processor is waiting to be released from + * the holding pen - release it, then wait for it to flag + * that it has been released by resetting pen_release. + * + * Note that "pen_release" is the hardware CPU ID, whereas + * "cpu" is Linux's internal ID. + */ + pen_release = cpu; + flush_cache_all(); + outer_flush_all(); + + timeout = jiffies + (1 * HZ); + while (time_before(jiffies, timeout)) { + smp_rmb(); + if (pen_release == -1) + break; + + udelay(10); + } + + /* + * now the secondary core is starting up let it run its + * calibrations, then wait for it to finish + */ + spin_unlock(&boot_lock); + + return pen_release != -1 ? -ENOSYS : 0; +} + +/* + * Initialise the CPU possible map early - this describes the CPUs + * which may be present or become present in the system. + */ +void __init smp_init_cpus(void) +{ + unsigned int i, ncores = scu_get_core_count(scu_base); + + if (ncores > nr_cpu_ids) { + pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", + ncores, nr_cpu_ids); + ncores = nr_cpu_ids; + } + + for (i = 0; i < ncores; i++) + set_cpu_possible(i, true); + + set_smp_cross_call(gic_raise_softirq); +} + +void __init platform_smp_prepare_cpus(unsigned int max_cpus) +{ + + scu_enable(scu_base); + + /* + * Write the address of secondary startup into the system-wide location + * (presently it is in SRAM). The BootMonitor waits until it receives a + * soft interrupt, and then the secondary CPU branches to this address. + */ + __raw_writel(virt_to_phys(spear13xx_secondary_startup), SYS_LOCATION); +} diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear13xx/spear1310.c new file mode 100644 index 000000000000..fefd15b2f380 --- /dev/null +++ b/arch/arm/mach-spear13xx/spear1310.c @@ -0,0 +1,88 @@ +/* + * arch/arm/mach-spear13xx/spear1310.c + * + * SPEAr1310 machine source file + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define pr_fmt(fmt) "SPEAr1310: " fmt + +#include <linux/amba/pl022.h> +#include <linux/of_platform.h> +#include <asm/hardware/gic.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <mach/generic.h> +#include <mach/spear.h> + +/* Base addresses */ +#define SPEAR1310_SSP1_BASE UL(0x5D400000) +#define SPEAR1310_SATA0_BASE UL(0xB1000000) +#define SPEAR1310_SATA1_BASE UL(0xB1800000) +#define SPEAR1310_SATA2_BASE UL(0xB4000000) + +/* ssp device registration */ +static struct pl022_ssp_controller ssp1_plat_data = { + .bus_id = 0, + .enable_dma = 0, + .num_chipselect = 3, +}; + +/* Add SPEAr1310 auxdata to pass platform data */ +static struct of_dev_auxdata spear1310_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv), + OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data), + OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data), + OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data), + + OF_DEV_AUXDATA("arm,pl022", SPEAR1310_SSP1_BASE, NULL, &ssp1_plat_data), + {} +}; + +static void __init spear1310_dt_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, + spear1310_auxdata_lookup, NULL); +} + +static const char * const spear1310_dt_board_compat[] = { + "st,spear1310", + "st,spear1310-evb", + NULL, +}; + +/* + * Following will create 16MB static virtual/physical mappings + * PHYSICAL VIRTUAL + * 0xD8000000 0xFA000000 + */ +struct map_desc spear1310_io_desc[] __initdata = { + { + .virtual = VA_SPEAR1310_RAS_GRP1_BASE, + .pfn = __phys_to_pfn(SPEAR1310_RAS_GRP1_BASE), + .length = SZ_16M, + .type = MT_DEVICE + }, +}; + +static void __init spear1310_map_io(void) +{ + iotable_init(spear1310_io_desc, ARRAY_SIZE(spear1310_io_desc)); + spear13xx_map_io(); +} + +DT_MACHINE_START(SPEAR1310_DT, "ST SPEAr1310 SoC with Flattened Device Tree") + .map_io = spear1310_map_io, + .init_irq = spear13xx_dt_init_irq, + .handle_irq = gic_handle_irq, + .timer = &spear13xx_timer, + .init_machine = spear1310_dt_init, + .restart = spear_restart, + .dt_compat = spear1310_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-spear13xx/spear1340.c b/arch/arm/mach-spear13xx/spear1340.c new file mode 100644 index 000000000000..ee38cbc56869 --- /dev/null +++ b/arch/arm/mach-spear13xx/spear1340.c @@ -0,0 +1,192 @@ +/* + * arch/arm/mach-spear13xx/spear1340.c + * + * SPEAr1340 machine source file + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define pr_fmt(fmt) "SPEAr1340: " fmt + +#include <linux/ahci_platform.h> +#include <linux/amba/serial.h> +#include <linux/delay.h> +#include <linux/dw_dmac.h> +#include <linux/of_platform.h> +#include <asm/hardware/gic.h> +#include <asm/mach/arch.h> +#include <mach/dma.h> +#include <mach/generic.h> +#include <mach/spear.h> + +/* Base addresses */ +#define SPEAR1340_SATA_BASE UL(0xB1000000) +#define SPEAR1340_UART1_BASE UL(0xB4100000) + +/* Power Management Registers */ +#define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100) +#define SPEAR1340_PCM_WKUP_CFG (VA_MISC_BASE + 0x104) +#define SPEAR1340_SWITCH_CTR (VA_MISC_BASE + 0x108) + +#define SPEAR1340_PERIP1_SW_RST (VA_MISC_BASE + 0x318) +#define SPEAR1340_PERIP2_SW_RST (VA_MISC_BASE + 0x31C) +#define SPEAR1340_PERIP3_SW_RST (VA_MISC_BASE + 0x320) + +/* PCIE - SATA configuration registers */ +#define SPEAR1340_PCIE_SATA_CFG (VA_MISC_BASE + 0x424) + /* PCIE CFG MASks */ + #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11) + #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10) + #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9) + #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8) + #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4) + #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3) + #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2) + #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1) + #define SPEAR1340_PCIE_SATA_SEL_PCIE (0) + #define SPEAR1340_PCIE_SATA_SEL_SATA (1) + #define SPEAR1340_SATA_PCIE_CFG_MASK 0xF1F + #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \ + SPEAR1340_PCIE_CFG_AUX_CLK_EN | \ + SPEAR1340_PCIE_CFG_CORE_CLK_EN | \ + SPEAR1340_PCIE_CFG_POWERUP_RESET | \ + SPEAR1340_PCIE_CFG_DEVICE_PRESENT) + #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \ + SPEAR1340_SATA_CFG_PM_CLK_EN | \ + SPEAR1340_SATA_CFG_POWERUP_RESET | \ + SPEAR1340_SATA_CFG_RX_CLK_EN | \ + SPEAR1340_SATA_CFG_TX_CLK_EN) + +#define SPEAR1340_PCIE_MIPHY_CFG (VA_MISC_BASE + 0x428) + #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31) + #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27) + #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27) + #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27) + #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0) + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \ + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ + SPEAR1340_MIPHY_CLK_REF_DIV2 | \ + SPEAR1340_MIPHY_PLL_RATIO_TOP(60)) + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \ + (SPEAR1340_MIPHY_PLL_RATIO_TOP(120)) + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \ + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ + SPEAR1340_MIPHY_PLL_RATIO_TOP(25)) + +static struct dw_dma_slave uart1_dma_param[] = { + { + /* Tx */ + .cfg_hi = DWC_CFGH_DST_PER(SPEAR1340_DMA_REQ_UART1_TX), + .cfg_lo = 0, + .src_master = DMA_MASTER_MEMORY, + .dst_master = SPEAR1340_DMA_MASTER_UART1, + }, { + /* Rx */ + .cfg_hi = DWC_CFGH_SRC_PER(SPEAR1340_DMA_REQ_UART1_RX), + .cfg_lo = 0, + .src_master = SPEAR1340_DMA_MASTER_UART1, + .dst_master = DMA_MASTER_MEMORY, + } +}; + +static struct amba_pl011_data uart1_data = { + .dma_filter = dw_dma_filter, + .dma_tx_param = &uart1_dma_param[0], + .dma_rx_param = &uart1_dma_param[1], +}; + +/* SATA device registration */ +static int sata_miphy_init(struct device *dev, void __iomem *addr) +{ + writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG); + writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK, + SPEAR1340_PCIE_MIPHY_CFG); + /* Switch on sata power domain */ + writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG); + msleep(20); + /* Disable PCIE SATA Controller reset */ + writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)), + SPEAR1340_PERIP1_SW_RST); + msleep(20); + + return 0; +} + +void sata_miphy_exit(struct device *dev) +{ + writel(0, SPEAR1340_PCIE_SATA_CFG); + writel(0, SPEAR1340_PCIE_MIPHY_CFG); + + /* Enable PCIE SATA Controller reset */ + writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)), + SPEAR1340_PERIP1_SW_RST); + msleep(20); + /* Switch off sata power domain */ + writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG); + msleep(20); +} + +int sata_suspend(struct device *dev) +{ + if (dev->power.power_state.event == PM_EVENT_FREEZE) + return 0; + + sata_miphy_exit(dev); + + return 0; +} + +int sata_resume(struct device *dev) +{ + if (dev->power.power_state.event == PM_EVENT_THAW) + return 0; + + return sata_miphy_init(dev, NULL); +} + +static struct ahci_platform_data sata_pdata = { + .init = sata_miphy_init, + .exit = sata_miphy_exit, + .suspend = sata_suspend, + .resume = sata_resume, +}; + +/* Add SPEAr1340 auxdata to pass platform data */ +static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv), + OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data), + OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data), + OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data), + + OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL, + &sata_pdata), + OF_DEV_AUXDATA("arm,pl011", SPEAR1340_UART1_BASE, NULL, &uart1_data), + {} +}; + +static void __init spear1340_dt_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, + spear1340_auxdata_lookup, NULL); +} + +static const char * const spear1340_dt_board_compat[] = { + "st,spear1340", + "st,spear1340-evb", + NULL, +}; + +DT_MACHINE_START(SPEAR1340_DT, "ST SPEAr1340 SoC with Flattened Device Tree") + .map_io = spear13xx_map_io, + .init_irq = spear13xx_dt_init_irq, + .handle_irq = gic_handle_irq, + .timer = &spear13xx_timer, + .init_machine = spear1340_dt_init, + .restart = spear_restart, + .dt_compat = spear1340_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c new file mode 100644 index 000000000000..50b349ae863d --- /dev/null +++ b/arch/arm/mach-spear13xx/spear13xx.c @@ -0,0 +1,197 @@ +/* + * arch/arm/mach-spear13xx/spear13xx.c + * + * SPEAr13XX machines common source file + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define pr_fmt(fmt) "SPEAr13xx: " fmt + +#include <linux/amba/pl022.h> +#include <linux/clk.h> +#include <linux/dw_dmac.h> +#include <linux/err.h> +#include <linux/of_irq.h> +#include <asm/hardware/cache-l2x0.h> +#include <asm/hardware/gic.h> +#include <asm/mach/map.h> +#include <asm/smp_twd.h> +#include <mach/dma.h> +#include <mach/generic.h> +#include <mach/spear.h> + +/* common dw_dma filter routine to be used by peripherals */ +bool dw_dma_filter(struct dma_chan *chan, void *slave) +{ + struct dw_dma_slave *dws = (struct dw_dma_slave *)slave; + + if (chan->device->dev == dws->dma_dev) { + chan->private = slave; + return true; + } else { + return false; + } +} + +/* ssp device registration */ +static struct dw_dma_slave ssp_dma_param[] = { + { + /* Tx */ + .cfg_hi = DWC_CFGH_DST_PER(DMA_REQ_SSP0_TX), + .cfg_lo = 0, + .src_master = DMA_MASTER_MEMORY, + .dst_master = DMA_MASTER_SSP0, + }, { + /* Rx */ + .cfg_hi = DWC_CFGH_SRC_PER(DMA_REQ_SSP0_RX), + .cfg_lo = 0, + .src_master = DMA_MASTER_SSP0, + .dst_master = DMA_MASTER_MEMORY, + } +}; + +struct pl022_ssp_controller pl022_plat_data = { + .bus_id = 0, + .enable_dma = 1, + .dma_filter = dw_dma_filter, + .dma_rx_param = &ssp_dma_param[1], + .dma_tx_param = &ssp_dma_param[0], + .num_chipselect = 3, +}; + +/* CF device registration */ +struct dw_dma_slave cf_dma_priv = { + .cfg_hi = 0, + .cfg_lo = 0, + .src_master = 0, + .dst_master = 0, +}; + +/* dmac device registeration */ +struct dw_dma_platform_data dmac_plat_data = { + .nr_channels = 8, + .chan_allocation_order = CHAN_ALLOCATION_DESCENDING, + .chan_priority = CHAN_PRIORITY_DESCENDING, +}; + +void __init spear13xx_l2x0_init(void) +{ + /* + * 512KB (64KB/way), 8-way associativity, parity supported + * + * FIXME: 9th bit, of Auxillary Controller register must be set + * for some spear13xx devices for stable L2 operation. + * + * Enable Early BRESP, L2 prefetch for Instruction and Data, + * write alloc and 'Full line of zero' options + * + */ + + writel_relaxed(0x06, VA_L2CC_BASE + L2X0_PREFETCH_CTRL); + + /* + * Program following latencies in order to make + * SPEAr1340 work at 600 MHz + */ + writel_relaxed(0x221, VA_L2CC_BASE + L2X0_TAG_LATENCY_CTRL); + writel_relaxed(0x441, VA_L2CC_BASE + L2X0_DATA_LATENCY_CTRL); + l2x0_init(VA_L2CC_BASE, 0x70A60001, 0xfe00ffff); +} + +/* + * Following will create 16MB static virtual/physical mappings + * PHYSICAL VIRTUAL + * 0xB3000000 0xFE000000 + * 0xE0000000 0xFD000000 + * 0xEC000000 0xFC000000 + * 0xED000000 0xFB000000 + */ +struct map_desc spear13xx_io_desc[] __initdata = { + { + .virtual = VA_PERIP_GRP2_BASE, + .pfn = __phys_to_pfn(PERIP_GRP2_BASE), + .length = SZ_16M, + .type = MT_DEVICE + }, { + .virtual = VA_PERIP_GRP1_BASE, + .pfn = __phys_to_pfn(PERIP_GRP1_BASE), + .length = SZ_16M, + .type = MT_DEVICE + }, { + .virtual = VA_A9SM_AND_MPMC_BASE, + .pfn = __phys_to_pfn(A9SM_AND_MPMC_BASE), + .length = SZ_16M, + .type = MT_DEVICE + }, { + .virtual = (unsigned long)VA_L2CC_BASE, + .pfn = __phys_to_pfn(L2CC_BASE), + .length = SZ_4K, + .type = MT_DEVICE + }, +}; + +/* This will create static memory mapping for selected devices */ +void __init spear13xx_map_io(void) +{ + iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc)); +} + +static void __init spear13xx_clk_init(void) +{ + if (of_machine_is_compatible("st,spear1310")) + spear1310_clk_init(); + else if (of_machine_is_compatible("st,spear1340")) + spear1340_clk_init(); + else + pr_err("%s: Unknown machine\n", __func__); +} + +static void __init spear13xx_timer_init(void) +{ + char pclk_name[] = "osc_24m_clk"; + struct clk *gpt_clk, *pclk; + + spear13xx_clk_init(); + + /* get the system timer clock */ + gpt_clk = clk_get_sys("gpt0", NULL); + if (IS_ERR(gpt_clk)) { + pr_err("%s:couldn't get clk for gpt\n", __func__); + BUG(); + } + + /* get the suitable parent clock for timer*/ + pclk = clk_get(NULL, pclk_name); + if (IS_ERR(pclk)) { + pr_err("%s:couldn't get %s as parent for gpt\n", __func__, + pclk_name); + BUG(); + } + + clk_set_parent(gpt_clk, pclk); + clk_put(gpt_clk); + clk_put(pclk); + + spear_setup_of_timer(); + twd_local_timer_of_register(); +} + +struct sys_timer spear13xx_timer = { + .init = spear13xx_timer_init, +}; + +static const struct of_device_id gic_of_match[] __initconst = { + { .compatible = "arm,cortex-a9-gic", .data = gic_of_init }, + { /* Sentinel */ } +}; + +void __init spear13xx_dt_init_irq(void) +{ + of_irq_init(gic_of_match); +} diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig index 2cee6b0de371..8bd37291fa4f 100644 --- a/arch/arm/mach-spear3xx/Kconfig +++ b/arch/arm/mach-spear3xx/Kconfig @@ -5,39 +5,22 @@ if ARCH_SPEAR3XX menu "SPEAr3xx Implementations" -config BOARD_SPEAR300_EVB - bool "SPEAr300 Evaluation Board" - select MACH_SPEAR300 - help - Supports ST SPEAr300 Evaluation Board - -config BOARD_SPEAR310_EVB - bool "SPEAr310 Evaluation Board" - select MACH_SPEAR310 - help - Supports ST SPEAr310 Evaluation Board - -config BOARD_SPEAR320_EVB - bool "SPEAr320 Evaluation Board" - select MACH_SPEAR320 - help - Supports ST SPEAr320 Evaluation Board - -endmenu - config MACH_SPEAR300 - bool "SPEAr300" + bool "SPEAr300 Machine support with Device Tree" + select PINCTRL_SPEAR300 help - Supports ST SPEAr300 Machine + Supports ST SPEAr300 machine configured via the device-tree config MACH_SPEAR310 - bool "SPEAr310" + bool "SPEAr310 Machine support with Device Tree" + select PINCTRL_SPEAR310 help - Supports ST SPEAr310 Machine + Supports ST SPEAr310 machine configured via the device-tree config MACH_SPEAR320 - bool "SPEAr320" + bool "SPEAr320 Machine support with Device Tree" + select PINCTRL_SPEAR320 help - Supports ST SPEAr320 Machine - + Supports ST SPEAr320 machine configured via the device-tree +endmenu endif #ARCH_SPEAR3XX diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile index b24862489704..8d12faa178fd 100644 --- a/arch/arm/mach-spear3xx/Makefile +++ b/arch/arm/mach-spear3xx/Makefile @@ -3,24 +3,13 @@ # # common files -obj-y += spear3xx.o clock.o +obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o # spear300 specific files obj-$(CONFIG_MACH_SPEAR300) += spear300.o -# spear300 boards files -obj-$(CONFIG_BOARD_SPEAR300_EVB) += spear300_evb.o - - # spear310 specific files obj-$(CONFIG_MACH_SPEAR310) += spear310.o -# spear310 boards files -obj-$(CONFIG_BOARD_SPEAR310_EVB) += spear310_evb.o - - # spear320 specific files obj-$(CONFIG_MACH_SPEAR320) += spear320.o - -# spear320 boards files -obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot index 4674a4c221db..d93e2177e6ec 100644 --- a/arch/arm/mach-spear3xx/Makefile.boot +++ b/arch/arm/mach-spear3xx/Makefile.boot @@ -1,3 +1,7 @@ zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 + +dtb-$(CONFIG_MACH_SPEAR300) += spear300-evb.dtb +dtb-$(CONFIG_MACH_SPEAR310) += spear310-evb.dtb +dtb-$(CONFIG_MACH_SPEAR320) += spear320-evb.dtb diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c deleted file mode 100644 index 6c4841f55223..000000000000 --- a/arch/arm/mach-spear3xx/clock.c +++ /dev/null @@ -1,760 +0,0 @@ -/* - * arch/arm/mach-spear3xx/clock.c - * - * SPEAr3xx machines clock framework source file - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/init.h> -#include <linux/io.h> -#include <linux/kernel.h> -#include <asm/mach-types.h> -#include <plat/clock.h> -#include <mach/misc_regs.h> - -/* root clks */ -/* 32 KHz oscillator clock */ -static struct clk osc_32k_clk = { - .flags = ALWAYS_ENABLED, - .rate = 32000, -}; - -/* 24 MHz oscillator clock */ -static struct clk osc_24m_clk = { - .flags = ALWAYS_ENABLED, - .rate = 24000000, -}; - -/* clock derived from 32 KHz osc clk */ -/* rtc clock */ -static struct clk rtc_clk = { - .pclk = &osc_32k_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = RTC_CLK_ENB, - .recalc = &follow_parent, -}; - -/* clock derived from 24 MHz osc clk */ -/* pll masks structure */ -static struct pll_clk_masks pll1_masks = { - .mode_mask = PLL_MODE_MASK, - .mode_shift = PLL_MODE_SHIFT, - .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK, - .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT, - .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK, - .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT, - .div_p_mask = PLL_DIV_P_MASK, - .div_p_shift = PLL_DIV_P_SHIFT, - .div_n_mask = PLL_DIV_N_MASK, - .div_n_shift = PLL_DIV_N_SHIFT, -}; - -/* pll1 configuration structure */ -static struct pll_clk_config pll1_config = { - .mode_reg = PLL1_CTR, - .cfg_reg = PLL1_FRQ, - .masks = &pll1_masks, -}; - -/* pll rate configuration table, in ascending order of rates */ -struct pll_rate_tbl pll_rtbl[] = { - {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */ - {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */ -}; - -/* PLL1 clock */ -static struct clk pll1_clk = { - .flags = ENABLED_ON_INIT, - .pclk = &osc_24m_clk, - .en_reg = PLL1_CTR, - .en_reg_bit = PLL_ENABLE, - .calc_rate = &pll_calc_rate, - .recalc = &pll_clk_recalc, - .set_rate = &pll_clk_set_rate, - .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1}, - .private_data = &pll1_config, -}; - -/* PLL3 48 MHz clock */ -static struct clk pll3_48m_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &osc_24m_clk, - .rate = 48000000, -}; - -/* watch dog timer clock */ -static struct clk wdt_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &osc_24m_clk, - .recalc = &follow_parent, -}; - -/* clock derived from pll1 clk */ -/* cpu clock */ -static struct clk cpu_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &pll1_clk, - .recalc = &follow_parent, -}; - -/* ahb masks structure */ -static struct bus_clk_masks ahb_masks = { - .mask = PLL_HCLK_RATIO_MASK, - .shift = PLL_HCLK_RATIO_SHIFT, -}; - -/* ahb configuration structure */ -static struct bus_clk_config ahb_config = { - .reg = CORE_CLK_CFG, - .masks = &ahb_masks, -}; - -/* ahb rate configuration table, in ascending order of rates */ -struct bus_rate_tbl bus_rtbl[] = { - {.div = 3}, /* == parent divided by 4 */ - {.div = 2}, /* == parent divided by 3 */ - {.div = 1}, /* == parent divided by 2 */ - {.div = 0}, /* == parent divided by 1 */ -}; - -/* ahb clock */ -static struct clk ahb_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &pll1_clk, - .calc_rate = &bus_calc_rate, - .recalc = &bus_clk_recalc, - .set_rate = &bus_clk_set_rate, - .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2}, - .private_data = &ahb_config, -}; - -/* auxiliary synthesizers masks */ -static struct aux_clk_masks aux_masks = { - .eq_sel_mask = AUX_EQ_SEL_MASK, - .eq_sel_shift = AUX_EQ_SEL_SHIFT, - .eq1_mask = AUX_EQ1_SEL, - .eq2_mask = AUX_EQ2_SEL, - .xscale_sel_mask = AUX_XSCALE_MASK, - .xscale_sel_shift = AUX_XSCALE_SHIFT, - .yscale_sel_mask = AUX_YSCALE_MASK, - .yscale_sel_shift = AUX_YSCALE_SHIFT, -}; - -/* uart synth configurations */ -static struct aux_clk_config uart_synth_config = { - .synth_reg = UART_CLK_SYNT, - .masks = &aux_masks, -}; - -/* aux rate configuration table, in ascending order of rates */ -struct aux_rate_tbl aux_rtbl[] = { - /* For PLL1 = 332 MHz */ - {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */ - {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */ - {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */ -}; - -/* uart synth clock */ -static struct clk uart_synth_clk = { - .en_reg = UART_CLK_SYNT, - .en_reg_bit = AUX_SYNT_ENB, - .pclk = &pll1_clk, - .calc_rate = &aux_calc_rate, - .recalc = &aux_clk_recalc, - .set_rate = &aux_clk_set_rate, - .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1}, - .private_data = &uart_synth_config, -}; - -/* uart parents */ -static struct pclk_info uart_pclk_info[] = { - { - .pclk = &uart_synth_clk, - .pclk_val = AUX_CLK_PLL1_VAL, - }, { - .pclk = &pll3_48m_clk, - .pclk_val = AUX_CLK_PLL3_VAL, - }, -}; - -/* uart parent select structure */ -static struct pclk_sel uart_pclk_sel = { - .pclk_info = uart_pclk_info, - .pclk_count = ARRAY_SIZE(uart_pclk_info), - .pclk_sel_reg = PERIP_CLK_CFG, - .pclk_sel_mask = UART_CLK_MASK, -}; - -/* uart clock */ -static struct clk uart_clk = { - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = UART_CLK_ENB, - .pclk_sel = &uart_pclk_sel, - .pclk_sel_shift = UART_CLK_SHIFT, - .recalc = &follow_parent, -}; - -/* firda configurations */ -static struct aux_clk_config firda_synth_config = { - .synth_reg = FIRDA_CLK_SYNT, - .masks = &aux_masks, -}; - -/* firda synth clock */ -static struct clk firda_synth_clk = { - .en_reg = FIRDA_CLK_SYNT, - .en_reg_bit = AUX_SYNT_ENB, - .pclk = &pll1_clk, - .calc_rate = &aux_calc_rate, - .recalc = &aux_clk_recalc, - .set_rate = &aux_clk_set_rate, - .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1}, - .private_data = &firda_synth_config, -}; - -/* firda parents */ -static struct pclk_info firda_pclk_info[] = { - { - .pclk = &firda_synth_clk, - .pclk_val = AUX_CLK_PLL1_VAL, - }, { - .pclk = &pll3_48m_clk, - .pclk_val = AUX_CLK_PLL3_VAL, - }, -}; - -/* firda parent select structure */ -static struct pclk_sel firda_pclk_sel = { - .pclk_info = firda_pclk_info, - .pclk_count = ARRAY_SIZE(firda_pclk_info), - .pclk_sel_reg = PERIP_CLK_CFG, - .pclk_sel_mask = FIRDA_CLK_MASK, -}; - -/* firda clock */ -static struct clk firda_clk = { - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = FIRDA_CLK_ENB, - .pclk_sel = &firda_pclk_sel, - .pclk_sel_shift = FIRDA_CLK_SHIFT, - .recalc = &follow_parent, -}; - -/* gpt synthesizer masks */ -static struct gpt_clk_masks gpt_masks = { - .mscale_sel_mask = GPT_MSCALE_MASK, - .mscale_sel_shift = GPT_MSCALE_SHIFT, - .nscale_sel_mask = GPT_NSCALE_MASK, - .nscale_sel_shift = GPT_NSCALE_SHIFT, -}; - -/* gpt rate configuration table, in ascending order of rates */ -struct gpt_rate_tbl gpt_rtbl[] = { - /* For pll1 = 332 MHz */ - {.mscale = 4, .nscale = 0}, /* 41.5 MHz */ - {.mscale = 2, .nscale = 0}, /* 55.3 MHz */ - {.mscale = 1, .nscale = 0}, /* 83 MHz */ -}; - -/* gpt0 synth clk config*/ -static struct gpt_clk_config gpt0_synth_config = { - .synth_reg = PRSC1_CLK_CFG, - .masks = &gpt_masks, -}; - -/* gpt synth clock */ -static struct clk gpt0_synth_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &pll1_clk, - .calc_rate = &gpt_calc_rate, - .recalc = &gpt_clk_recalc, - .set_rate = &gpt_clk_set_rate, - .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2}, - .private_data = &gpt0_synth_config, -}; - -/* gpt parents */ -static struct pclk_info gpt0_pclk_info[] = { - { - .pclk = &gpt0_synth_clk, - .pclk_val = AUX_CLK_PLL1_VAL, - }, { - .pclk = &pll3_48m_clk, - .pclk_val = AUX_CLK_PLL3_VAL, - }, -}; - -/* gpt parent select structure */ -static struct pclk_sel gpt0_pclk_sel = { - .pclk_info = gpt0_pclk_info, - .pclk_count = ARRAY_SIZE(gpt0_pclk_info), - .pclk_sel_reg = PERIP_CLK_CFG, - .pclk_sel_mask = GPT_CLK_MASK, -}; - -/* gpt0 timer clock */ -static struct clk gpt0_clk = { - .flags = ALWAYS_ENABLED, - .pclk_sel = &gpt0_pclk_sel, - .pclk_sel_shift = GPT0_CLK_SHIFT, - .recalc = &follow_parent, -}; - -/* gpt1 synth clk configurations */ -static struct gpt_clk_config gpt1_synth_config = { - .synth_reg = PRSC2_CLK_CFG, - .masks = &gpt_masks, -}; - -/* gpt1 synth clock */ -static struct clk gpt1_synth_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &pll1_clk, - .calc_rate = &gpt_calc_rate, - .recalc = &gpt_clk_recalc, - .set_rate = &gpt_clk_set_rate, - .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2}, - .private_data = &gpt1_synth_config, -}; - -static struct pclk_info gpt1_pclk_info[] = { - { - .pclk = &gpt1_synth_clk, - .pclk_val = AUX_CLK_PLL1_VAL, - }, { - .pclk = &pll3_48m_clk, - .pclk_val = AUX_CLK_PLL3_VAL, - }, -}; - -/* gpt parent select structure */ -static struct pclk_sel gpt1_pclk_sel = { - .pclk_info = gpt1_pclk_info, - .pclk_count = ARRAY_SIZE(gpt1_pclk_info), - .pclk_sel_reg = PERIP_CLK_CFG, - .pclk_sel_mask = GPT_CLK_MASK, -}; - -/* gpt1 timer clock */ -static struct clk gpt1_clk = { - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = GPT1_CLK_ENB, - .pclk_sel = &gpt1_pclk_sel, - .pclk_sel_shift = GPT1_CLK_SHIFT, - .recalc = &follow_parent, -}; - -/* gpt2 synth clk configurations */ -static struct gpt_clk_config gpt2_synth_config = { - .synth_reg = PRSC3_CLK_CFG, - .masks = &gpt_masks, -}; - -/* gpt1 synth clock */ -static struct clk gpt2_synth_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &pll1_clk, - .calc_rate = &gpt_calc_rate, - .recalc = &gpt_clk_recalc, - .set_rate = &gpt_clk_set_rate, - .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2}, - .private_data = &gpt2_synth_config, -}; - -static struct pclk_info gpt2_pclk_info[] = { - { - .pclk = &gpt2_synth_clk, - .pclk_val = AUX_CLK_PLL1_VAL, - }, { - .pclk = &pll3_48m_clk, - .pclk_val = AUX_CLK_PLL3_VAL, - }, -}; - -/* gpt parent select structure */ -static struct pclk_sel gpt2_pclk_sel = { - .pclk_info = gpt2_pclk_info, - .pclk_count = ARRAY_SIZE(gpt2_pclk_info), - .pclk_sel_reg = PERIP_CLK_CFG, - .pclk_sel_mask = GPT_CLK_MASK, -}; - -/* gpt2 timer clock */ -static struct clk gpt2_clk = { - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = GPT2_CLK_ENB, - .pclk_sel = &gpt2_pclk_sel, - .pclk_sel_shift = GPT2_CLK_SHIFT, - .recalc = &follow_parent, -}; - -/* clock derived from pll3 clk */ -/* usbh clock */ -static struct clk usbh_clk = { - .pclk = &pll3_48m_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = USBH_CLK_ENB, - .recalc = &follow_parent, -}; - -/* usbd clock */ -static struct clk usbd_clk = { - .pclk = &pll3_48m_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = USBD_CLK_ENB, - .recalc = &follow_parent, -}; - -/* clock derived from ahb clk */ -/* apb masks structure */ -static struct bus_clk_masks apb_masks = { - .mask = HCLK_PCLK_RATIO_MASK, - .shift = HCLK_PCLK_RATIO_SHIFT, -}; - -/* apb configuration structure */ -static struct bus_clk_config apb_config = { - .reg = CORE_CLK_CFG, - .masks = &apb_masks, -}; - -/* apb clock */ -static struct clk apb_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &ahb_clk, - .calc_rate = &bus_calc_rate, - .recalc = &bus_clk_recalc, - .set_rate = &bus_clk_set_rate, - .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2}, - .private_data = &apb_config, -}; - -/* i2c clock */ -static struct clk i2c_clk = { - .pclk = &ahb_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = I2C_CLK_ENB, - .recalc = &follow_parent, -}; - -/* dma clock */ -static struct clk dma_clk = { - .pclk = &ahb_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = DMA_CLK_ENB, - .recalc = &follow_parent, -}; - -/* jpeg clock */ -static struct clk jpeg_clk = { - .pclk = &ahb_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = JPEG_CLK_ENB, - .recalc = &follow_parent, -}; - -/* gmac clock */ -static struct clk gmac_clk = { - .pclk = &ahb_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = GMAC_CLK_ENB, - .recalc = &follow_parent, -}; - -/* smi clock */ -static struct clk smi_clk = { - .pclk = &ahb_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = SMI_CLK_ENB, - .recalc = &follow_parent, -}; - -/* c3 clock */ -static struct clk c3_clk = { - .pclk = &ahb_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = C3_CLK_ENB, - .recalc = &follow_parent, -}; - -/* clock derived from apb clk */ -/* adc clock */ -static struct clk adc_clk = { - .pclk = &apb_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = ADC_CLK_ENB, - .recalc = &follow_parent, -}; - -#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) -/* emi clock */ -static struct clk emi_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &ahb_clk, - .recalc = &follow_parent, -}; -#endif - -/* ssp clock */ -static struct clk ssp0_clk = { - .pclk = &apb_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = SSP_CLK_ENB, - .recalc = &follow_parent, -}; - -/* gpio clock */ -static struct clk gpio_clk = { - .pclk = &apb_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = GPIO_CLK_ENB, - .recalc = &follow_parent, -}; - -static struct clk dummy_apb_pclk; - -#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \ - defined(CONFIG_MACH_SPEAR320) -/* fsmc clock */ -static struct clk fsmc_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &ahb_clk, - .recalc = &follow_parent, -}; -#endif - -/* common clocks to spear310 and spear320 */ -#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) -/* uart1 clock */ -static struct clk uart1_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &apb_clk, - .recalc = &follow_parent, -}; - -/* uart2 clock */ -static struct clk uart2_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &apb_clk, - .recalc = &follow_parent, -}; -#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */ - -/* common clocks to spear300 and spear320 */ -#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320) -/* clcd clock */ -static struct clk clcd_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &pll3_48m_clk, - .recalc = &follow_parent, -}; - -/* sdhci clock */ -static struct clk sdhci_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &ahb_clk, - .recalc = &follow_parent, -}; -#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */ - -/* spear300 machine specific clock structures */ -#ifdef CONFIG_MACH_SPEAR300 -/* gpio1 clock */ -static struct clk gpio1_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &apb_clk, - .recalc = &follow_parent, -}; - -/* keyboard clock */ -static struct clk kbd_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &apb_clk, - .recalc = &follow_parent, -}; - -#endif - -/* spear310 machine specific clock structures */ -#ifdef CONFIG_MACH_SPEAR310 -/* uart3 clock */ -static struct clk uart3_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &apb_clk, - .recalc = &follow_parent, -}; - -/* uart4 clock */ -static struct clk uart4_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &apb_clk, - .recalc = &follow_parent, -}; - -/* uart5 clock */ -static struct clk uart5_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &apb_clk, - .recalc = &follow_parent, -}; -#endif - -/* spear320 machine specific clock structures */ -#ifdef CONFIG_MACH_SPEAR320 -/* can0 clock */ -static struct clk can0_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &apb_clk, - .recalc = &follow_parent, -}; - -/* can1 clock */ -static struct clk can1_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &apb_clk, - .recalc = &follow_parent, -}; - -/* i2c1 clock */ -static struct clk i2c1_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &ahb_clk, - .recalc = &follow_parent, -}; - -/* ssp1 clock */ -static struct clk ssp1_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &apb_clk, - .recalc = &follow_parent, -}; - -/* ssp2 clock */ -static struct clk ssp2_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &apb_clk, - .recalc = &follow_parent, -}; - -/* pwm clock */ -static struct clk pwm_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &apb_clk, - .recalc = &follow_parent, -}; -#endif - -/* array of all spear 3xx clock lookups */ -static struct clk_lookup spear_clk_lookups[] = { - { .con_id = "apb_pclk", .clk = &dummy_apb_pclk}, - /* root clks */ - { .con_id = "osc_32k_clk", .clk = &osc_32k_clk}, - { .con_id = "osc_24m_clk", .clk = &osc_24m_clk}, - /* clock derived from 32 KHz osc clk */ - { .dev_id = "rtc-spear", .clk = &rtc_clk}, - /* clock derived from 24 MHz osc clk */ - { .con_id = "pll1_clk", .clk = &pll1_clk}, - { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk}, - { .dev_id = "wdt", .clk = &wdt_clk}, - /* clock derived from pll1 clk */ - { .con_id = "cpu_clk", .clk = &cpu_clk}, - { .con_id = "ahb_clk", .clk = &ahb_clk}, - { .con_id = "uart_synth_clk", .clk = &uart_synth_clk}, - { .con_id = "firda_synth_clk", .clk = &firda_synth_clk}, - { .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk}, - { .con_id = "gpt1_synth_clk", .clk = &gpt1_synth_clk}, - { .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk}, - { .dev_id = "uart", .clk = &uart_clk}, - { .dev_id = "firda", .clk = &firda_clk}, - { .dev_id = "gpt0", .clk = &gpt0_clk}, - { .dev_id = "gpt1", .clk = &gpt1_clk}, - { .dev_id = "gpt2", .clk = &gpt2_clk}, - /* clock derived from pll3 clk */ - { .dev_id = "designware_udc", .clk = &usbd_clk}, - { .con_id = "usbh_clk", .clk = &usbh_clk}, - /* clock derived from ahb clk */ - { .con_id = "apb_clk", .clk = &apb_clk}, - { .dev_id = "i2c_designware.0", .clk = &i2c_clk}, - { .dev_id = "dma", .clk = &dma_clk}, - { .dev_id = "jpeg", .clk = &jpeg_clk}, - { .dev_id = "gmac", .clk = &gmac_clk}, - { .dev_id = "smi", .clk = &smi_clk}, - { .dev_id = "c3", .clk = &c3_clk}, - /* clock derived from apb clk */ - { .dev_id = "adc", .clk = &adc_clk}, - { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk}, - { .dev_id = "gpio", .clk = &gpio_clk}, -}; - -/* array of all spear 300 clock lookups */ -#ifdef CONFIG_MACH_SPEAR300 -static struct clk_lookup spear300_clk_lookups[] = { - { .dev_id = "clcd", .clk = &clcd_clk}, - { .con_id = "fsmc", .clk = &fsmc_clk}, - { .dev_id = "gpio1", .clk = &gpio1_clk}, - { .dev_id = "keyboard", .clk = &kbd_clk}, - { .dev_id = "sdhci", .clk = &sdhci_clk}, -}; -#endif - -/* array of all spear 310 clock lookups */ -#ifdef CONFIG_MACH_SPEAR310 -static struct clk_lookup spear310_clk_lookups[] = { - { .con_id = "fsmc", .clk = &fsmc_clk}, - { .con_id = "emi", .clk = &emi_clk}, - { .dev_id = "uart1", .clk = &uart1_clk}, - { .dev_id = "uart2", .clk = &uart2_clk}, - { .dev_id = "uart3", .clk = &uart3_clk}, - { .dev_id = "uart4", .clk = &uart4_clk}, - { .dev_id = "uart5", .clk = &uart5_clk}, -}; -#endif - -/* array of all spear 320 clock lookups */ -#ifdef CONFIG_MACH_SPEAR320 -static struct clk_lookup spear320_clk_lookups[] = { - { .dev_id = "clcd", .clk = &clcd_clk}, - { .con_id = "fsmc", .clk = &fsmc_clk}, - { .dev_id = "i2c_designware.1", .clk = &i2c1_clk}, - { .con_id = "emi", .clk = &emi_clk}, - { .dev_id = "pwm", .clk = &pwm_clk}, - { .dev_id = "sdhci", .clk = &sdhci_clk}, - { .dev_id = "c_can_platform.0", .clk = &can0_clk}, - { .dev_id = "c_can_platform.1", .clk = &can1_clk}, - { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk}, - { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk}, - { .dev_id = "uart1", .clk = &uart1_clk}, - { .dev_id = "uart2", .clk = &uart2_clk}, -}; -#endif - -void __init spear3xx_clk_init(void) -{ - int i, cnt; - struct clk_lookup *lookups; - - if (machine_is_spear300()) { - cnt = ARRAY_SIZE(spear300_clk_lookups); - lookups = spear300_clk_lookups; - } else if (machine_is_spear310()) { - cnt = ARRAY_SIZE(spear310_clk_lookups); - lookups = spear310_clk_lookups; - } else { - cnt = ARRAY_SIZE(spear320_clk_lookups); - lookups = spear320_clk_lookups; - } - - for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) - clk_register(&spear_clk_lookups[i]); - - for (i = 0; i < cnt; i++) - clk_register(&lookups[i]); - - clk_init(); -} diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h index 14276e5a98d2..4a95b9453c2a 100644 --- a/arch/arm/mach-spear3xx/include/mach/generic.h +++ b/arch/arm/mach-spear3xx/include/mach/generic.h @@ -14,189 +14,24 @@ #ifndef __MACH_GENERIC_H #define __MACH_GENERIC_H +#include <linux/amba/pl08x.h> #include <linux/init.h> #include <linux/platform_device.h> #include <linux/amba/bus.h> #include <asm/mach/time.h> #include <asm/mach/map.h> -#include <plat/padmux.h> - -/* spear3xx declarations */ -/* - * Each GPT has 2 timer channels - * Following GPT channels will be used as clock source and clockevent - */ -#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE -#define SPEAR_GPT0_CHAN0_IRQ SPEAR3XX_IRQ_CPU_GPT1_1 -#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2 /* Add spear3xx family device structure declarations here */ -extern struct amba_device spear3xx_gpio_device; -extern struct amba_device spear3xx_uart_device; extern struct sys_timer spear3xx_timer; +extern struct pl022_ssp_controller pl022_plat_data; +extern struct pl08x_platform_data pl080_plat_data; /* Add spear3xx family function declarations here */ +void __init spear_setup_of_timer(void); void __init spear3xx_clk_init(void); -void __init spear_setup_timer(void); void __init spear3xx_map_io(void); -void __init spear3xx_init_irq(void); -void __init spear3xx_init(void); +void __init spear3xx_dt_init_irq(void); void spear_restart(char, const char *); -/* pad mux declarations */ -#define PMX_FIRDA_MASK (1 << 14) -#define PMX_I2C_MASK (1 << 13) -#define PMX_SSP_CS_MASK (1 << 12) -#define PMX_SSP_MASK (1 << 11) -#define PMX_MII_MASK (1 << 10) -#define PMX_GPIO_PIN0_MASK (1 << 9) -#define PMX_GPIO_PIN1_MASK (1 << 8) -#define PMX_GPIO_PIN2_MASK (1 << 7) -#define PMX_GPIO_PIN3_MASK (1 << 6) -#define PMX_GPIO_PIN4_MASK (1 << 5) -#define PMX_GPIO_PIN5_MASK (1 << 4) -#define PMX_UART0_MODEM_MASK (1 << 3) -#define PMX_UART0_MASK (1 << 2) -#define PMX_TIMER_3_4_MASK (1 << 1) -#define PMX_TIMER_1_2_MASK (1 << 0) - -/* pad mux devices */ -extern struct pmx_dev spear3xx_pmx_firda; -extern struct pmx_dev spear3xx_pmx_i2c; -extern struct pmx_dev spear3xx_pmx_ssp_cs; -extern struct pmx_dev spear3xx_pmx_ssp; -extern struct pmx_dev spear3xx_pmx_mii; -extern struct pmx_dev spear3xx_pmx_gpio_pin0; -extern struct pmx_dev spear3xx_pmx_gpio_pin1; -extern struct pmx_dev spear3xx_pmx_gpio_pin2; -extern struct pmx_dev spear3xx_pmx_gpio_pin3; -extern struct pmx_dev spear3xx_pmx_gpio_pin4; -extern struct pmx_dev spear3xx_pmx_gpio_pin5; -extern struct pmx_dev spear3xx_pmx_uart0_modem; -extern struct pmx_dev spear3xx_pmx_uart0; -extern struct pmx_dev spear3xx_pmx_timer_3_4; -extern struct pmx_dev spear3xx_pmx_timer_1_2; - -#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) -/* padmux plgpio devices */ -extern struct pmx_dev spear3xx_pmx_plgpio_0_1; -extern struct pmx_dev spear3xx_pmx_plgpio_2_3; -extern struct pmx_dev spear3xx_pmx_plgpio_4_5; -extern struct pmx_dev spear3xx_pmx_plgpio_6_9; -extern struct pmx_dev spear3xx_pmx_plgpio_10_27; -extern struct pmx_dev spear3xx_pmx_plgpio_28; -extern struct pmx_dev spear3xx_pmx_plgpio_29; -extern struct pmx_dev spear3xx_pmx_plgpio_30; -extern struct pmx_dev spear3xx_pmx_plgpio_31; -extern struct pmx_dev spear3xx_pmx_plgpio_32; -extern struct pmx_dev spear3xx_pmx_plgpio_33; -extern struct pmx_dev spear3xx_pmx_plgpio_34_36; -extern struct pmx_dev spear3xx_pmx_plgpio_37_42; -extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48; -extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50; -#endif - -/* spear300 declarations */ -#ifdef CONFIG_MACH_SPEAR300 -/* Add spear300 machine device structure declarations here */ -extern struct amba_device spear300_gpio1_device; - -/* pad mux modes */ -extern struct pmx_mode spear300_nand_mode; -extern struct pmx_mode spear300_nor_mode; -extern struct pmx_mode spear300_photo_frame_mode; -extern struct pmx_mode spear300_lend_ip_phone_mode; -extern struct pmx_mode spear300_hend_ip_phone_mode; -extern struct pmx_mode spear300_lend_wifi_phone_mode; -extern struct pmx_mode spear300_hend_wifi_phone_mode; -extern struct pmx_mode spear300_ata_pabx_wi2s_mode; -extern struct pmx_mode spear300_ata_pabx_i2s_mode; -extern struct pmx_mode spear300_caml_lcdw_mode; -extern struct pmx_mode spear300_camu_lcd_mode; -extern struct pmx_mode spear300_camu_wlcd_mode; -extern struct pmx_mode spear300_caml_lcd_mode; - -/* pad mux devices */ -extern struct pmx_dev spear300_pmx_fsmc_2_chips; -extern struct pmx_dev spear300_pmx_fsmc_4_chips; -extern struct pmx_dev spear300_pmx_keyboard; -extern struct pmx_dev spear300_pmx_clcd; -extern struct pmx_dev spear300_pmx_telecom_gpio; -extern struct pmx_dev spear300_pmx_telecom_tdm; -extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk; -extern struct pmx_dev spear300_pmx_telecom_camera; -extern struct pmx_dev spear300_pmx_telecom_dac; -extern struct pmx_dev spear300_pmx_telecom_i2s; -extern struct pmx_dev spear300_pmx_telecom_boot_pins; -extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit; -extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit; -extern struct pmx_dev spear300_pmx_gpio1; - -/* Add spear300 machine function declarations here */ -void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, - u8 pmx_dev_count); - -#endif /* CONFIG_MACH_SPEAR300 */ - -/* spear310 declarations */ -#ifdef CONFIG_MACH_SPEAR310 -/* Add spear310 machine device structure declarations here */ - -/* pad mux devices */ -extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5; -extern struct pmx_dev spear310_pmx_emi_cs_2_3; -extern struct pmx_dev spear310_pmx_uart1; -extern struct pmx_dev spear310_pmx_uart2; -extern struct pmx_dev spear310_pmx_uart3_4_5; -extern struct pmx_dev spear310_pmx_fsmc; -extern struct pmx_dev spear310_pmx_rs485_0_1; -extern struct pmx_dev spear310_pmx_tdm0; - -/* Add spear310 machine function declarations here */ -void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, - u8 pmx_dev_count); - -#endif /* CONFIG_MACH_SPEAR310 */ - -/* spear320 declarations */ -#ifdef CONFIG_MACH_SPEAR320 -/* Add spear320 machine device structure declarations here */ - -/* pad mux modes */ -extern struct pmx_mode spear320_auto_net_smii_mode; -extern struct pmx_mode spear320_auto_net_mii_mode; -extern struct pmx_mode spear320_auto_exp_mode; -extern struct pmx_mode spear320_small_printers_mode; - -/* pad mux devices */ -extern struct pmx_dev spear320_pmx_clcd; -extern struct pmx_dev spear320_pmx_emi; -extern struct pmx_dev spear320_pmx_fsmc; -extern struct pmx_dev spear320_pmx_spp; -extern struct pmx_dev spear320_pmx_sdhci; -extern struct pmx_dev spear320_pmx_i2s; -extern struct pmx_dev spear320_pmx_uart1; -extern struct pmx_dev spear320_pmx_uart1_modem; -extern struct pmx_dev spear320_pmx_uart2; -extern struct pmx_dev spear320_pmx_touchscreen; -extern struct pmx_dev spear320_pmx_can; -extern struct pmx_dev spear320_pmx_sdhci_led; -extern struct pmx_dev spear320_pmx_pwm0; -extern struct pmx_dev spear320_pmx_pwm1; -extern struct pmx_dev spear320_pmx_pwm2; -extern struct pmx_dev spear320_pmx_pwm3; -extern struct pmx_dev spear320_pmx_ssp1; -extern struct pmx_dev spear320_pmx_ssp2; -extern struct pmx_dev spear320_pmx_mii1; -extern struct pmx_dev spear320_pmx_smii0; -extern struct pmx_dev spear320_pmx_smii1; -extern struct pmx_dev spear320_pmx_i2c1; - -/* Add spear320 machine function declarations here */ -void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, - u8 pmx_dev_count); - -#endif /* CONFIG_MACH_SPEAR320 */ - #endif /* __MACH_GENERIC_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h index 4660c0d8ec0d..40a8c178f10d 100644 --- a/arch/arm/mach-spear3xx/include/mach/hardware.h +++ b/arch/arm/mach-spear3xx/include/mach/hardware.h @@ -1,23 +1 @@ -/* - * arch/arm/mach-spear3xx/include/mach/hardware.h - * - * Hardware definitions for SPEAr3xx machine family - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_HARDWARE_H -#define __MACH_HARDWARE_H - -#include <plat/hardware.h> -#include <mach/spear.h> - -/* Vitual to physical translation of statically mapped space */ -#define IO_ADDRESS(x) (x | 0xF0000000) - -#endif /* __MACH_HARDWARE_H */ +/* empty */ diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h index 6e265442808e..51bd62a0254c 100644 --- a/arch/arm/mach-spear3xx/include/mach/irqs.h +++ b/arch/arm/mach-spear3xx/include/mach/irqs.h @@ -14,141 +14,14 @@ #ifndef __MACH_IRQS_H #define __MACH_IRQS_H -/* SPEAr3xx IRQ definitions */ -#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0 0 +/* FIXME: probe all these from DT */ #define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1 -#define SPEAR3XX_IRQ_CPU_GPT1_1 2 -#define SPEAR3XX_IRQ_CPU_GPT1_2 3 -#define SPEAR3XX_IRQ_BASIC_GPT1_1 4 -#define SPEAR3XX_IRQ_BASIC_GPT1_2 5 -#define SPEAR3XX_IRQ_BASIC_GPT2_1 6 -#define SPEAR3XX_IRQ_BASIC_GPT2_2 7 -#define SPEAR3XX_IRQ_BASIC_DMA 8 -#define SPEAR3XX_IRQ_BASIC_SMI 9 -#define SPEAR3XX_IRQ_BASIC_RTC 10 -#define SPEAR3XX_IRQ_BASIC_GPIO 11 -#define SPEAR3XX_IRQ_BASIC_WDT 12 -#define SPEAR3XX_IRQ_DDR_CONTROLLER 13 -#define SPEAR3XX_IRQ_SYS_ERROR 14 -#define SPEAR3XX_IRQ_WAKEUP_RCV 15 -#define SPEAR3XX_IRQ_JPEG 16 -#define SPEAR3XX_IRQ_IRDA 17 -#define SPEAR3XX_IRQ_ADC 18 -#define SPEAR3XX_IRQ_UART 19 -#define SPEAR3XX_IRQ_SSP 20 -#define SPEAR3XX_IRQ_I2C 21 -#define SPEAR3XX_IRQ_MAC_1 22 -#define SPEAR3XX_IRQ_MAC_2 23 -#define SPEAR3XX_IRQ_USB_DEV 24 -#define SPEAR3XX_IRQ_USB_H_OHCI_0 25 -#define SPEAR3XX_IRQ_USB_H_EHCI_0 26 -#define SPEAR3XX_IRQ_USB_H_EHCI_1 SPEAR3XX_IRQ_USB_H_EHCI_0 -#define SPEAR3XX_IRQ_USB_H_OHCI_1 27 #define SPEAR3XX_IRQ_GEN_RAS_1 28 #define SPEAR3XX_IRQ_GEN_RAS_2 29 #define SPEAR3XX_IRQ_GEN_RAS_3 30 -#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1 31 #define SPEAR3XX_IRQ_VIC_END 32 - #define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END -/* SPEAr300 Virtual irq definitions */ -/* IRQs sharing IRQ_GEN_RAS_1 */ -#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0) -#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1) -#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2) -#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3) -#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4) -#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5) -#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6) -#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7) -#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8) - -/* IRQs sharing IRQ_GEN_RAS_3 */ -#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3 - -/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ -#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM - -/* SPEAr310 Virtual irq definitions */ -/* IRQs sharing IRQ_GEN_RAS_1 */ -#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0) -#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1) -#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2) -#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3) -#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4) -#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5) -#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6) -#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7) - -/* IRQs sharing IRQ_GEN_RAS_2 */ -#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8) -#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9) -#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10) -#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11) -#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12) - -/* IRQs sharing IRQ_GEN_RAS_3 */ -#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13) -#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14) - -/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ -#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15) -#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16) -#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17) - -/* SPEAr320 Virtual irq definitions */ -/* IRQs sharing IRQ_GEN_RAS_1 */ -#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0) -#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1) -#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2) - -/* IRQs sharing IRQ_GEN_RAS_2 */ -#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2 - -/* IRQs sharing IRQ_GEN_RAS_3 */ -#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3) -#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4) -#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5) - -/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ -#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6) -#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7) -#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8) -#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9) -#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10) -#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11) -#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12) -#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13) -#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14) -#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15) -#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16) - -/* - * GPIO pins virtual irqs - * Use the lowest number for the GPIO virtual IRQs base on which subarchs - * we have compiled in - */ -#if defined(CONFIG_MACH_SPEAR310) -#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 18) -#elif defined(CONFIG_MACH_SPEAR320) -#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 17) -#else -#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 9) -#endif - -#define SPEAR300_GPIO1_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8) -#define SPEAR3XX_PLGPIO_COUNT 102 - -#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) -#define SPEAR3XX_PLGPIO_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8) -#define SPEAR3XX_GPIO_INT_END (SPEAR3XX_PLGPIO_INT_BASE + \ - SPEAR3XX_PLGPIO_COUNT) -#else -#define SPEAR3XX_GPIO_INT_END (SPEAR300_GPIO1_INT_BASE + 8) -#endif - -#define SPEAR3XX_VIRQ_END SPEAR3XX_GPIO_INT_END -#define NR_IRQS SPEAR3XX_VIRQ_END +#define NR_IRQS 160 #endif /* __MACH_IRQS_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h index 5bd8cd8d4852..18e2ac576f25 100644 --- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h +++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h @@ -14,151 +14,9 @@ #ifndef __MACH_MISC_REGS_H #define __MACH_MISC_REGS_H -#include <mach/hardware.h> +#include <mach/spear.h> #define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE) - -#define SOC_CFG_CTR (MISC_BASE + 0x000) -#define DIAG_CFG_CTR (MISC_BASE + 0x004) -#define PLL1_CTR (MISC_BASE + 0x008) -#define PLL1_FRQ (MISC_BASE + 0x00C) -#define PLL1_MOD (MISC_BASE + 0x010) -#define PLL2_CTR (MISC_BASE + 0x014) -/* PLL_CTR register masks */ -#define PLL_ENABLE 2 -#define PLL_MODE_SHIFT 4 -#define PLL_MODE_MASK 0x3 -#define PLL_MODE_NORMAL 0 -#define PLL_MODE_FRACTION 1 -#define PLL_MODE_DITH_DSB 2 -#define PLL_MODE_DITH_SSB 3 - -#define PLL2_FRQ (MISC_BASE + 0x018) -/* PLL FRQ register masks */ -#define PLL_DIV_N_SHIFT 0 -#define PLL_DIV_N_MASK 0xFF -#define PLL_DIV_P_SHIFT 8 -#define PLL_DIV_P_MASK 0x7 -#define PLL_NORM_FDBK_M_SHIFT 24 -#define PLL_NORM_FDBK_M_MASK 0xFF -#define PLL_DITH_FDBK_M_SHIFT 16 -#define PLL_DITH_FDBK_M_MASK 0xFFFF - -#define PLL2_MOD (MISC_BASE + 0x01C) -#define PLL_CLK_CFG (MISC_BASE + 0x020) -#define CORE_CLK_CFG (MISC_BASE + 0x024) -/* CORE CLK CFG register masks */ -#define PLL_HCLK_RATIO_SHIFT 10 -#define PLL_HCLK_RATIO_MASK 0x3 -#define HCLK_PCLK_RATIO_SHIFT 8 -#define HCLK_PCLK_RATIO_MASK 0x3 - -#define PERIP_CLK_CFG (MISC_BASE + 0x028) -/* PERIP_CLK_CFG register masks */ -#define UART_CLK_SHIFT 4 -#define UART_CLK_MASK 0x1 -#define FIRDA_CLK_SHIFT 5 -#define FIRDA_CLK_MASK 0x3 -#define GPT0_CLK_SHIFT 8 -#define GPT1_CLK_SHIFT 11 -#define GPT2_CLK_SHIFT 12 -#define GPT_CLK_MASK 0x1 -#define AUX_CLK_PLL3_VAL 0 -#define AUX_CLK_PLL1_VAL 1 - -#define PERIP1_CLK_ENB (MISC_BASE + 0x02C) -/* PERIP1_CLK_ENB register masks */ -#define UART_CLK_ENB 3 -#define SSP_CLK_ENB 5 -#define I2C_CLK_ENB 7 -#define JPEG_CLK_ENB 8 -#define FIRDA_CLK_ENB 10 -#define GPT1_CLK_ENB 11 -#define GPT2_CLK_ENB 12 -#define ADC_CLK_ENB 15 -#define RTC_CLK_ENB 17 -#define GPIO_CLK_ENB 18 -#define DMA_CLK_ENB 19 -#define SMI_CLK_ENB 21 -#define GMAC_CLK_ENB 23 -#define USBD_CLK_ENB 24 -#define USBH_CLK_ENB 25 -#define C3_CLK_ENB 31 - -#define SOC_CORE_ID (MISC_BASE + 0x030) -#define RAS_CLK_ENB (MISC_BASE + 0x034) -#define PERIP1_SOF_RST (MISC_BASE + 0x038) -/* PERIP1_SOF_RST register masks */ -#define JPEG_SOF_RST 8 - -#define SOC_USER_ID (MISC_BASE + 0x03C) -#define RAS_SOF_RST (MISC_BASE + 0x040) -#define PRSC1_CLK_CFG (MISC_BASE + 0x044) -#define PRSC2_CLK_CFG (MISC_BASE + 0x048) -#define PRSC3_CLK_CFG (MISC_BASE + 0x04C) -/* gpt synthesizer register masks */ -#define GPT_MSCALE_SHIFT 0 -#define GPT_MSCALE_MASK 0xFFF -#define GPT_NSCALE_SHIFT 12 -#define GPT_NSCALE_MASK 0xF - -#define AMEM_CLK_CFG (MISC_BASE + 0x050) -#define EXPI_CLK_CFG (MISC_BASE + 0x054) -#define CLCD_CLK_SYNT (MISC_BASE + 0x05C) -#define FIRDA_CLK_SYNT (MISC_BASE + 0x060) -#define UART_CLK_SYNT (MISC_BASE + 0x064) -#define GMAC_CLK_SYNT (MISC_BASE + 0x068) -#define RAS1_CLK_SYNT (MISC_BASE + 0x06C) -#define RAS2_CLK_SYNT (MISC_BASE + 0x070) -#define RAS3_CLK_SYNT (MISC_BASE + 0x074) -#define RAS4_CLK_SYNT (MISC_BASE + 0x078) -/* aux clk synthesiser register masks for irda to ras4 */ -#define AUX_SYNT_ENB 31 -#define AUX_EQ_SEL_SHIFT 30 -#define AUX_EQ_SEL_MASK 1 -#define AUX_EQ1_SEL 0 -#define AUX_EQ2_SEL 1 -#define AUX_XSCALE_SHIFT 16 -#define AUX_XSCALE_MASK 0xFFF -#define AUX_YSCALE_SHIFT 0 -#define AUX_YSCALE_MASK 0xFFF - -#define ICM1_ARB_CFG (MISC_BASE + 0x07C) -#define ICM2_ARB_CFG (MISC_BASE + 0x080) -#define ICM3_ARB_CFG (MISC_BASE + 0x084) -#define ICM4_ARB_CFG (MISC_BASE + 0x088) -#define ICM5_ARB_CFG (MISC_BASE + 0x08C) -#define ICM6_ARB_CFG (MISC_BASE + 0x090) -#define ICM7_ARB_CFG (MISC_BASE + 0x094) -#define ICM8_ARB_CFG (MISC_BASE + 0x098) -#define ICM9_ARB_CFG (MISC_BASE + 0x09C) #define DMA_CHN_CFG (MISC_BASE + 0x0A0) -#define USB2_PHY_CFG (MISC_BASE + 0x0A4) -#define GMAC_CFG_CTR (MISC_BASE + 0x0A8) -#define EXPI_CFG_CTR (MISC_BASE + 0x0AC) -#define PRC1_LOCK_CTR (MISC_BASE + 0x0C0) -#define PRC2_LOCK_CTR (MISC_BASE + 0x0C4) -#define PRC3_LOCK_CTR (MISC_BASE + 0x0C8) -#define PRC4_LOCK_CTR (MISC_BASE + 0x0CC) -#define PRC1_IRQ_CTR (MISC_BASE + 0x0D0) -#define PRC2_IRQ_CTR (MISC_BASE + 0x0D4) -#define PRC3_IRQ_CTR (MISC_BASE + 0x0D8) -#define PRC4_IRQ_CTR (MISC_BASE + 0x0DC) -#define PWRDOWN_CFG_CTR (MISC_BASE + 0x0E0) -#define COMPSSTL_1V8_CFG (MISC_BASE + 0x0E4) -#define COMPSSTL_2V5_CFG (MISC_BASE + 0x0E8) -#define COMPCOR_3V3_CFG (MISC_BASE + 0x0EC) -#define SSTLPAD_CFG_CTR (MISC_BASE + 0x0F0) -#define BIST1_CFG_CTR (MISC_BASE + 0x0F4) -#define BIST2_CFG_CTR (MISC_BASE + 0x0F8) -#define BIST3_CFG_CTR (MISC_BASE + 0x0FC) -#define BIST4_CFG_CTR (MISC_BASE + 0x100) -#define BIST5_CFG_CTR (MISC_BASE + 0x104) -#define BIST1_STS_RES (MISC_BASE + 0x108) -#define BIST2_STS_RES (MISC_BASE + 0x10C) -#define BIST3_STS_RES (MISC_BASE + 0x110) -#define BIST4_STS_RES (MISC_BASE + 0x114) -#define BIST5_STS_RES (MISC_BASE + 0x118) -#define SYSERR_CFG_CTR (MISC_BASE + 0x11C) #endif /* __MACH_MISC_REGS_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h index 63fd98356919..51eb953148a9 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear.h +++ b/arch/arm/mach-spear3xx/include/mach/spear.h @@ -15,60 +15,26 @@ #define __MACH_SPEAR3XX_H #include <asm/memory.h> -#include <mach/spear300.h> -#include <mach/spear310.h> -#include <mach/spear320.h> - -#define SPEAR3XX_ML_SDRAM_BASE UL(0x00000000) - -#define SPEAR3XX_ICM9_BASE UL(0xC0000000) /* ICM1 - Low speed connection */ #define SPEAR3XX_ICM1_2_BASE UL(0xD0000000) +#define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000) #define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000) -#define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE) -#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000) +#define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE) #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) -#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000) -#define SPEAR3XX_ICM1_JPEG_BASE UL(0xD0800000) -#define SPEAR3XX_ICM1_IRDA_BASE UL(0xD1000000) -#define SPEAR3XX_ICM1_SRAM_BASE UL(0xD2800000) - -/* ICM2 - Application Subsystem */ -#define SPEAR3XX_ICM2_HWACCEL0_BASE UL(0xD8800000) -#define SPEAR3XX_ICM2_HWACCEL1_BASE UL(0xD9000000) - -/* ICM4 - High Speed Connection */ -#define SPEAR3XX_ICM4_BASE UL(0xE0000000) -#define SPEAR3XX_ICM4_MII_BASE UL(0xE0800000) -#define SPEAR3XX_ICM4_USBD_FIFO_BASE UL(0xE1000000) -#define SPEAR3XX_ICM4_USBD_CSR_BASE UL(0xE1100000) -#define SPEAR3XX_ICM4_USBD_PLDT_BASE UL(0xE1200000) -#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE UL(0xE1800000) -#define SPEAR3XX_ICM4_USB_OHCI0_BASE UL(0xE1900000) -#define SPEAR3XX_ICM4_USB_OHCI1_BASE UL(0xE2100000) -#define SPEAR3XX_ICM4_USB_ARB_BASE UL(0xE2800000) /* ML1 - Multi Layer CPU Subsystem */ #define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000) -#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000) -#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000) -#define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE) +#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000) /* ICM3 - Basic Subsystem */ -#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000) #define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) +#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) #define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000) -#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000) -#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000) -#define SPEAR3XX_ICM3_WDT_BASE UL(0xFC880000) -#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000) -#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000) #define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) -#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE) +#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE) #define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000) -#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE) -#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000) +#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE) /* Debug uart for linux, will be used for debug and uncompress messages */ #define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE @@ -78,4 +44,17 @@ #define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE #define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE +/* SPEAr320 Macros */ +#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) +#define VA_SPEAR320_SOC_CONFIG_BASE UL(0xFE000000) +#define SPEAR320_CONTROL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE) +#define SPEAR320_EXT_CTRL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018) + #define SPEAR320_UARTX_PCLK_MASK 0x1 + #define SPEAR320_UART2_PCLK_SHIFT 8 + #define SPEAR320_UART3_PCLK_SHIFT 9 + #define SPEAR320_UART4_PCLK_SHIFT 10 + #define SPEAR320_UART5_PCLK_SHIFT 11 + #define SPEAR320_UART6_PCLK_SHIFT 12 + #define SPEAR320_RS485_PCLK_SHIFT 13 + #endif /* __MACH_SPEAR3XX_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h deleted file mode 100644 index 3b6ea0729040..000000000000 --- a/arch/arm/mach-spear3xx/include/mach/spear300.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * arch/arm/mach-spear3xx/include/mach/spear300.h - * - * SPEAr300 Machine specific definition - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifdef CONFIG_MACH_SPEAR300 - -#ifndef __MACH_SPEAR300_H -#define __MACH_SPEAR300_H - -/* Base address of various IPs */ -#define SPEAR300_TELECOM_BASE UL(0x50000000) - -/* Interrupt registers offsets and masks */ -#define SPEAR300_INT_ENB_MASK_REG 0x54 -#define SPEAR300_INT_STS_MASK_REG 0x58 -#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0) -#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1) -#define SPEAR300_I2S_IRQ_MASK (1 << 2) -#define SPEAR300_TDM_IRQ_MASK (1 << 3) -#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4) -#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5) -#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6) -#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7) -#define SPEAR300_GPIO1_IRQ_MASK (1 << 8) - -#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF - -#define SPEAR300_CLCD_BASE UL(0x60000000) -#define SPEAR300_SDHCI_BASE UL(0x70000000) -#define SPEAR300_NAND_0_BASE UL(0x80000000) -#define SPEAR300_NAND_1_BASE UL(0x84000000) -#define SPEAR300_NAND_2_BASE UL(0x88000000) -#define SPEAR300_NAND_3_BASE UL(0x8c000000) -#define SPEAR300_NOR_0_BASE UL(0x90000000) -#define SPEAR300_NOR_1_BASE UL(0x91000000) -#define SPEAR300_NOR_2_BASE UL(0x92000000) -#define SPEAR300_NOR_3_BASE UL(0x93000000) -#define SPEAR300_FSMC_BASE UL(0x94000000) -#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000) -#define SPEAR300_KEYBOARD_BASE UL(0xA0000000) -#define SPEAR300_GPIO_BASE UL(0xA9000000) - -#endif /* __MACH_SPEAR300_H */ - -#endif /* CONFIG_MACH_SPEAR300 */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h deleted file mode 100644 index 1567d0da725f..000000000000 --- a/arch/arm/mach-spear3xx/include/mach/spear310.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * arch/arm/mach-spear3xx/include/mach/spear310.h - * - * SPEAr310 Machine specific definition - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifdef CONFIG_MACH_SPEAR310 - -#ifndef __MACH_SPEAR310_H -#define __MACH_SPEAR310_H - -#define SPEAR310_NAND_BASE UL(0x40000000) -#define SPEAR310_FSMC_BASE UL(0x44000000) -#define SPEAR310_UART1_BASE UL(0xB2000000) -#define SPEAR310_UART2_BASE UL(0xB2080000) -#define SPEAR310_UART3_BASE UL(0xB2100000) -#define SPEAR310_UART4_BASE UL(0xB2180000) -#define SPEAR310_UART5_BASE UL(0xB2200000) -#define SPEAR310_HDLC_BASE UL(0xB2800000) -#define SPEAR310_RS485_0_BASE UL(0xB3000000) -#define SPEAR310_RS485_1_BASE UL(0xB3800000) -#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000) - -/* Interrupt registers offsets and masks */ -#define SPEAR310_INT_STS_MASK_REG 0x04 -#define SPEAR310_SMII0_IRQ_MASK (1 << 0) -#define SPEAR310_SMII1_IRQ_MASK (1 << 1) -#define SPEAR310_SMII2_IRQ_MASK (1 << 2) -#define SPEAR310_SMII3_IRQ_MASK (1 << 3) -#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4) -#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5) -#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6) -#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7) -#define SPEAR310_UART1_IRQ_MASK (1 << 8) -#define SPEAR310_UART2_IRQ_MASK (1 << 9) -#define SPEAR310_UART3_IRQ_MASK (1 << 10) -#define SPEAR310_UART4_IRQ_MASK (1 << 11) -#define SPEAR310_UART5_IRQ_MASK (1 << 12) -#define SPEAR310_EMI_IRQ_MASK (1 << 13) -#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14) -#define SPEAR310_RS485_0_IRQ_MASK (1 << 15) -#define SPEAR310_RS485_1_IRQ_MASK (1 << 16) - -#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF -#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00 -#define SPEAR310_SHIRQ_RAS3_MASK 0x02000 -#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000 - -#endif /* __MACH_SPEAR310_H */ - -#endif /* CONFIG_MACH_SPEAR310 */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h deleted file mode 100644 index 8cfa83fa1296..000000000000 --- a/arch/arm/mach-spear3xx/include/mach/spear320.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * arch/arm/mach-spear3xx/include/mach/spear320.h - * - * SPEAr320 Machine specific definition - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifdef CONFIG_MACH_SPEAR320 - -#ifndef __MACH_SPEAR320_H -#define __MACH_SPEAR320_H - -#define SPEAR320_EMI_CTRL_BASE UL(0x40000000) -#define SPEAR320_FSMC_BASE UL(0x4C000000) -#define SPEAR320_NAND_BASE UL(0x50000000) -#define SPEAR320_I2S_BASE UL(0x60000000) -#define SPEAR320_SDHCI_BASE UL(0x70000000) -#define SPEAR320_CLCD_BASE UL(0x90000000) -#define SPEAR320_PAR_PORT_BASE UL(0xA0000000) -#define SPEAR320_CAN0_BASE UL(0xA1000000) -#define SPEAR320_CAN1_BASE UL(0xA2000000) -#define SPEAR320_UART1_BASE UL(0xA3000000) -#define SPEAR320_UART2_BASE UL(0xA4000000) -#define SPEAR320_SSP0_BASE UL(0xA5000000) -#define SPEAR320_SSP1_BASE UL(0xA6000000) -#define SPEAR320_I2C_BASE UL(0xA7000000) -#define SPEAR320_PWM_BASE UL(0xA8000000) -#define SPEAR320_SMII0_BASE UL(0xAA000000) -#define SPEAR320_SMII1_BASE UL(0xAB000000) -#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) - -/* Interrupt registers offsets and masks */ -#define SPEAR320_INT_STS_MASK_REG 0x04 -#define SPEAR320_INT_CLR_MASK_REG 0x04 -#define SPEAR320_INT_ENB_MASK_REG 0x08 -#define SPEAR320_GPIO_IRQ_MASK (1 << 0) -#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1) -#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2) -#define SPEAR320_EMI_IRQ_MASK (1 << 7) -#define SPEAR320_CLCD_IRQ_MASK (1 << 8) -#define SPEAR320_SPP_IRQ_MASK (1 << 9) -#define SPEAR320_SDHCI_IRQ_MASK (1 << 10) -#define SPEAR320_CAN_U_IRQ_MASK (1 << 11) -#define SPEAR320_CAN_L_IRQ_MASK (1 << 12) -#define SPEAR320_UART1_IRQ_MASK (1 << 13) -#define SPEAR320_UART2_IRQ_MASK (1 << 14) -#define SPEAR320_SSP1_IRQ_MASK (1 << 15) -#define SPEAR320_SSP2_IRQ_MASK (1 << 16) -#define SPEAR320_SMII0_IRQ_MASK (1 << 17) -#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18) -#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19) -#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20) -#define SPEAR320_I2C1_IRQ_MASK (1 << 21) - -#define SPEAR320_SHIRQ_RAS1_MASK 0x000380 -#define SPEAR320_SHIRQ_RAS3_MASK 0x000007 -#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800 - -#endif /* __MACH_SPEAR320_H */ - -#endif /* CONFIG_MACH_SPEAR320 */ diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c index f7db66812abb..f74a05bdb829 100644 --- a/arch/arm/mach-spear3xx/spear300.c +++ b/arch/arm/mach-spear3xx/spear300.c @@ -3,372 +3,62 @@ * * SPEAr300 machine source file * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> + * Copyright (C) 2009-2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#include <linux/types.h> -#include <linux/amba/pl061.h> -#include <linux/ptrace.h> -#include <asm/irq.h> +#define pr_fmt(fmt) "SPEAr300: " fmt + +#include <linux/amba/pl08x.h> +#include <linux/of_platform.h> +#include <asm/hardware/vic.h> +#include <asm/mach/arch.h> #include <plat/shirq.h> #include <mach/generic.h> -#include <mach/hardware.h> - -/* pad multiplexing support */ -/* muxing registers */ -#define PAD_MUX_CONFIG_REG 0x00 -#define MODE_CONFIG_REG 0x04 - -/* modes */ -#define NAND_MODE (1 << 0) -#define NOR_MODE (1 << 1) -#define PHOTO_FRAME_MODE (1 << 2) -#define LEND_IP_PHONE_MODE (1 << 3) -#define HEND_IP_PHONE_MODE (1 << 4) -#define LEND_WIFI_PHONE_MODE (1 << 5) -#define HEND_WIFI_PHONE_MODE (1 << 6) -#define ATA_PABX_WI2S_MODE (1 << 7) -#define ATA_PABX_I2S_MODE (1 << 8) -#define CAML_LCDW_MODE (1 << 9) -#define CAMU_LCD_MODE (1 << 10) -#define CAMU_WLCD_MODE (1 << 11) -#define CAML_LCD_MODE (1 << 12) -#define ALL_MODES 0x1FFF - -struct pmx_mode spear300_nand_mode = { - .id = NAND_MODE, - .name = "nand mode", - .mask = 0x00, -}; - -struct pmx_mode spear300_nor_mode = { - .id = NOR_MODE, - .name = "nor mode", - .mask = 0x01, -}; - -struct pmx_mode spear300_photo_frame_mode = { - .id = PHOTO_FRAME_MODE, - .name = "photo frame mode", - .mask = 0x02, -}; - -struct pmx_mode spear300_lend_ip_phone_mode = { - .id = LEND_IP_PHONE_MODE, - .name = "lend ip phone mode", - .mask = 0x03, -}; - -struct pmx_mode spear300_hend_ip_phone_mode = { - .id = HEND_IP_PHONE_MODE, - .name = "hend ip phone mode", - .mask = 0x04, -}; - -struct pmx_mode spear300_lend_wifi_phone_mode = { - .id = LEND_WIFI_PHONE_MODE, - .name = "lend wifi phone mode", - .mask = 0x05, -}; - -struct pmx_mode spear300_hend_wifi_phone_mode = { - .id = HEND_WIFI_PHONE_MODE, - .name = "hend wifi phone mode", - .mask = 0x06, -}; - -struct pmx_mode spear300_ata_pabx_wi2s_mode = { - .id = ATA_PABX_WI2S_MODE, - .name = "ata pabx wi2s mode", - .mask = 0x07, -}; - -struct pmx_mode spear300_ata_pabx_i2s_mode = { - .id = ATA_PABX_I2S_MODE, - .name = "ata pabx i2s mode", - .mask = 0x08, -}; - -struct pmx_mode spear300_caml_lcdw_mode = { - .id = CAML_LCDW_MODE, - .name = "caml lcdw mode", - .mask = 0x0C, -}; - -struct pmx_mode spear300_camu_lcd_mode = { - .id = CAMU_LCD_MODE, - .name = "camu lcd mode", - .mask = 0x0D, -}; - -struct pmx_mode spear300_camu_wlcd_mode = { - .id = CAMU_WLCD_MODE, - .name = "camu wlcd mode", - .mask = 0x0E, -}; - -struct pmx_mode spear300_caml_lcd_mode = { - .id = CAML_LCD_MODE, - .name = "caml lcd mode", - .mask = 0x0F, -}; - -/* devices */ -static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = { - { - .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | - ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, - .mask = PMX_FIRDA_MASK, - }, -}; - -struct pmx_dev spear300_pmx_fsmc_2_chips = { - .name = "fsmc_2_chips", - .modes = pmx_fsmc_2_chips_modes, - .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = { - { - .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | - ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, - .mask = PMX_FIRDA_MASK | PMX_UART0_MASK, - }, -}; - -struct pmx_dev spear300_pmx_fsmc_4_chips = { - .name = "fsmc_4_chips", - .modes = pmx_fsmc_4_chips_modes, - .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_keyboard_modes[] = { - { - .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | - LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | - CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE | - CAML_LCD_MODE, - .mask = 0x0, - }, -}; - -struct pmx_dev spear300_pmx_keyboard = { - .name = "keyboard", - .modes = pmx_keyboard_modes, - .mode_count = ARRAY_SIZE(pmx_keyboard_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_clcd_modes[] = { - { - .ids = PHOTO_FRAME_MODE, - .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK , - }, { - .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE | - CAMU_LCD_MODE | CAML_LCD_MODE, - .mask = PMX_TIMER_3_4_MASK, - }, -}; - -struct pmx_dev spear300_pmx_clcd = { - .name = "clcd", - .modes = pmx_clcd_modes, - .mode_count = ARRAY_SIZE(pmx_clcd_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_telecom_gpio_modes[] = { - { - .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE, - .mask = PMX_MII_MASK, - }, { - .ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE, - .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, - }, { - .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE, - .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK, - }, { - .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE, - .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK, - }, { - .ids = ATA_PABX_WI2S_MODE, - .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK - | PMX_UART0_MODEM_MASK, - }, -}; - -struct pmx_dev spear300_pmx_telecom_gpio = { - .name = "telecom_gpio", - .modes = pmx_telecom_gpio_modes, - .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_telecom_tdm_modes[] = { - { - .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | - HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE - | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE - | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE - | CAMU_WLCD_MODE | CAML_LCD_MODE, - .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK, - }, -}; - -struct pmx_dev spear300_pmx_telecom_tdm = { - .name = "telecom_tdm", - .modes = pmx_telecom_tdm_modes, - .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = { - { - .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | - LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE - | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | - CAML_LCDW_MODE | CAML_LCD_MODE, - .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, - }, -}; - -struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = { - .name = "telecom_spi_cs_i2c_clk", - .modes = pmx_telecom_spi_cs_i2c_clk_modes, - .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_telecom_camera_modes[] = { - { - .ids = CAML_LCDW_MODE | CAML_LCD_MODE, - .mask = PMX_MII_MASK, - }, { - .ids = CAMU_LCD_MODE | CAMU_WLCD_MODE, - .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK, - }, -}; - -struct pmx_dev spear300_pmx_telecom_camera = { - .name = "telecom_camera", - .modes = pmx_telecom_camera_modes, - .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_telecom_dac_modes[] = { - { - .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE - | CAMU_WLCD_MODE | CAML_LCD_MODE, - .mask = PMX_TIMER_1_2_MASK, - }, -}; - -struct pmx_dev spear300_pmx_telecom_dac = { - .name = "telecom_dac", - .modes = pmx_telecom_dac_modes, - .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_telecom_i2s_modes[] = { - { - .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE - | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | - ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE - | CAMU_WLCD_MODE | CAML_LCD_MODE, - .mask = PMX_UART0_MODEM_MASK, - }, -}; - -struct pmx_dev spear300_pmx_telecom_i2s = { - .name = "telecom_i2s", - .modes = pmx_telecom_i2s_modes, - .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = { - { - .ids = NAND_MODE | NOR_MODE, - .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK | - PMX_TIMER_3_4_MASK, - }, -}; - -struct pmx_dev spear300_pmx_telecom_boot_pins = { - .name = "telecom_boot_pins", - .modes = pmx_telecom_boot_pins_modes, - .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = { - { - .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | - HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | - HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | - CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE | - ATA_PABX_I2S_MODE, - .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | - PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | - PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, - }, -}; - -struct pmx_dev spear300_pmx_telecom_sdhci_4bit = { - .name = "telecom_sdhci_4bit", - .modes = pmx_telecom_sdhci_4bit_modes, - .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = { - { - .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | - HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | - HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | - CAMU_WLCD_MODE | CAML_LCD_MODE, - .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | - PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | - PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK, - }, -}; - -struct pmx_dev spear300_pmx_telecom_sdhci_8bit = { - .name = "telecom_sdhci_8bit", - .modes = pmx_telecom_sdhci_8bit_modes, - .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_gpio1_modes[] = { - { - .ids = PHOTO_FRAME_MODE, - .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK | - PMX_TIMER_3_4_MASK, - }, -}; - -struct pmx_dev spear300_pmx_gpio1 = { - .name = "arm gpio1", - .modes = pmx_gpio1_modes, - .mode_count = ARRAY_SIZE(pmx_gpio1_modes), - .enb_on_reset = 1, -}; - -/* pmx driver structure */ -static struct pmx_driver pmx_driver = { - .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f}, - .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, -}; +#include <mach/spear.h> + +/* Base address of various IPs */ +#define SPEAR300_TELECOM_BASE UL(0x50000000) + +/* Interrupt registers offsets and masks */ +#define SPEAR300_INT_ENB_MASK_REG 0x54 +#define SPEAR300_INT_STS_MASK_REG 0x58 +#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0) +#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1) +#define SPEAR300_I2S_IRQ_MASK (1 << 2) +#define SPEAR300_TDM_IRQ_MASK (1 << 3) +#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4) +#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5) +#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6) +#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7) +#define SPEAR300_GPIO1_IRQ_MASK (1 << 8) + +#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF + +#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000) + + +/* SPEAr300 Virtual irq definitions */ +/* IRQs sharing IRQ_GEN_RAS_1 */ +#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0) +#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1) +#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2) +#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3) +#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4) +#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5) +#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6) +#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7) +#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8) + +/* IRQs sharing IRQ_GEN_RAS_3 */ +#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3 + +/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ +#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM /* spear3xx shared irq */ static struct shirq_dev_config shirq_ras1_config[] = { @@ -423,45 +113,238 @@ static struct spear_shirq shirq_ras1 = { }, }; -/* Add spear300 specific devices here */ -/* arm gpio1 device registration */ -static struct pl061_platform_data gpio1_plat_data = { - .gpio_base = 8, - .irq_base = SPEAR300_GPIO1_INT_BASE, +/* DMAC platform data's slave info */ +struct pl08x_channel_data spear300_dma_info[] = { + { + .bus_id = "uart0_rx", + .min_signal = 2, + .max_signal = 2, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart0_tx", + .min_signal = 3, + .max_signal = 3, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ssp0_rx", + .min_signal = 8, + .max_signal = 8, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ssp0_tx", + .min_signal = 9, + .max_signal = 9, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "i2c_rx", + .min_signal = 10, + .max_signal = 10, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "i2c_tx", + .min_signal = 11, + .max_signal = 11, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "irda", + .min_signal = 12, + .max_signal = 12, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "adc", + .min_signal = 13, + .max_signal = 13, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "to_jpeg", + .min_signal = 14, + .max_signal = 14, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "from_jpeg", + .min_signal = 15, + .max_signal = 15, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras0_rx", + .min_signal = 0, + .max_signal = 0, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras0_tx", + .min_signal = 1, + .max_signal = 1, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras1_rx", + .min_signal = 2, + .max_signal = 2, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras1_tx", + .min_signal = 3, + .max_signal = 3, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras2_rx", + .min_signal = 4, + .max_signal = 4, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras2_tx", + .min_signal = 5, + .max_signal = 5, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras3_rx", + .min_signal = 6, + .max_signal = 6, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras3_tx", + .min_signal = 7, + .max_signal = 7, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras4_rx", + .min_signal = 8, + .max_signal = 8, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras4_tx", + .min_signal = 9, + .max_signal = 9, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras5_rx", + .min_signal = 10, + .max_signal = 10, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras5_tx", + .min_signal = 11, + .max_signal = 11, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras6_rx", + .min_signal = 12, + .max_signal = 12, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras6_tx", + .min_signal = 13, + .max_signal = 13, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras7_rx", + .min_signal = 14, + .max_signal = 14, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras7_tx", + .min_signal = 15, + .max_signal = 15, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, }; -AMBA_APB_DEVICE(spear300_gpio1, "gpio1", 0, SPEAR300_GPIO_BASE, - {SPEAR300_VIRQ_GPIO1}, &gpio1_plat_data); +/* Add SPEAr300 auxdata to pass platform data */ +static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, + &pl022_plat_data), + OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL, + &pl080_plat_data), + {} +}; -/* spear300 routines */ -void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, - u8 pmx_dev_count) +static void __init spear300_dt_init(void) { - int ret = 0; + int ret; + + pl080_plat_data.slave_channels = spear300_dma_info; + pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info); - /* call spear3xx family common init function */ - spear3xx_init(); + of_platform_populate(NULL, of_default_bus_match_table, + spear300_auxdata_lookup, NULL); /* shared irq registration */ shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K); if (shirq_ras1.regs.base) { ret = spear_shirq_register(&shirq_ras1); if (ret) - printk(KERN_ERR "Error registering Shared IRQ\n"); + pr_err("Error registering Shared IRQ\n"); } +} - /* pmx initialization */ - pmx_driver.mode = pmx_mode; - pmx_driver.devs = pmx_devs; - pmx_driver.devs_count = pmx_dev_count; +static const char * const spear300_dt_board_compat[] = { + "st,spear300", + "st,spear300-evb", + NULL, +}; - pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K); - if (pmx_driver.base) { - ret = pmx_register(&pmx_driver); - if (ret) - printk(KERN_ERR "padmux: registration failed. err no" - ": %d\n", ret); - /* Free Mapping, device selection already done */ - iounmap(pmx_driver.base); - } +static void __init spear300_map_io(void) +{ + spear3xx_map_io(); } + +DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree") + .map_io = spear300_map_io, + .init_irq = spear3xx_dt_init_irq, + .handle_irq = vic_handle_irq, + .timer = &spear3xx_timer, + .init_machine = spear300_dt_init, + .restart = spear_restart, + .dt_compat = spear300_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c deleted file mode 100644 index 3462ab9d6122..000000000000 --- a/arch/arm/mach-spear3xx/spear300_evb.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * arch/arm/mach-spear3xx/spear300_evb.c - * - * SPEAr300 evaluation board source file - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <asm/hardware/vic.h> -#include <asm/mach/arch.h> -#include <asm/mach-types.h> -#include <mach/generic.h> -#include <mach/hardware.h> - -/* padmux devices to enable */ -static struct pmx_dev *pmx_devs[] = { - /* spear3xx specific devices */ - &spear3xx_pmx_i2c, - &spear3xx_pmx_ssp_cs, - &spear3xx_pmx_ssp, - &spear3xx_pmx_mii, - &spear3xx_pmx_uart0, - - /* spear300 specific devices */ - &spear300_pmx_fsmc_2_chips, - &spear300_pmx_clcd, - &spear300_pmx_telecom_sdhci_4bit, - &spear300_pmx_gpio1, -}; - -static struct amba_device *amba_devs[] __initdata = { - /* spear3xx specific devices */ - &spear3xx_gpio_device, - &spear3xx_uart_device, - - /* spear300 specific devices */ - &spear300_gpio1_device, -}; - -static struct platform_device *plat_devs[] __initdata = { - /* spear3xx specific devices */ - - /* spear300 specific devices */ -}; - -static void __init spear300_evb_init(void) -{ - unsigned int i; - - /* call spear300 machine init function */ - spear300_init(&spear300_photo_frame_mode, pmx_devs, - ARRAY_SIZE(pmx_devs)); - - /* Add Platform Devices */ - platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); - - /* Add Amba Devices */ - for (i = 0; i < ARRAY_SIZE(amba_devs); i++) - amba_device_register(amba_devs[i], &iomem_resource); -} - -MACHINE_START(SPEAR300, "ST-SPEAR300-EVB") - .atag_offset = 0x100, - .map_io = spear3xx_map_io, - .init_irq = spear3xx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &spear3xx_timer, - .init_machine = spear300_evb_init, - .restart = spear_restart, -MACHINE_END diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c index febaa6fcfb6a..84dfb0900747 100644 --- a/arch/arm/mach-spear3xx/spear310.c +++ b/arch/arm/mach-spear3xx/spear310.c @@ -3,141 +3,84 @@ * * SPEAr310 machine source file * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> + * Copyright (C) 2009-2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#include <linux/ptrace.h> -#include <asm/irq.h> +#define pr_fmt(fmt) "SPEAr310: " fmt + +#include <linux/amba/pl08x.h> +#include <linux/amba/serial.h> +#include <linux/of_platform.h> +#include <asm/hardware/vic.h> +#include <asm/mach/arch.h> #include <plat/shirq.h> #include <mach/generic.h> -#include <mach/hardware.h> - -/* pad multiplexing support */ -/* muxing registers */ -#define PAD_MUX_CONFIG_REG 0x08 - -/* devices */ -static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = { - { - .ids = 0x00, - .mask = PMX_TIMER_3_4_MASK, - }, -}; - -struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = { - .name = "emi_cs_0_1_4_5", - .modes = pmx_emi_cs_0_1_4_5_modes, - .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = { - { - .ids = 0x00, - .mask = PMX_TIMER_1_2_MASK, - }, -}; - -struct pmx_dev spear310_pmx_emi_cs_2_3 = { - .name = "emi_cs_2_3", - .modes = pmx_emi_cs_2_3_modes, - .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_uart1_modes[] = { - { - .ids = 0x00, - .mask = PMX_FIRDA_MASK, - }, -}; - -struct pmx_dev spear310_pmx_uart1 = { - .name = "uart1", - .modes = pmx_uart1_modes, - .mode_count = ARRAY_SIZE(pmx_uart1_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_uart2_modes[] = { - { - .ids = 0x00, - .mask = PMX_TIMER_1_2_MASK, - }, -}; - -struct pmx_dev spear310_pmx_uart2 = { - .name = "uart2", - .modes = pmx_uart2_modes, - .mode_count = ARRAY_SIZE(pmx_uart2_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_uart3_4_5_modes[] = { - { - .ids = 0x00, - .mask = PMX_UART0_MODEM_MASK, - }, -}; - -struct pmx_dev spear310_pmx_uart3_4_5 = { - .name = "uart3_4_5", - .modes = pmx_uart3_4_5_modes, - .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_fsmc_modes[] = { - { - .ids = 0x00, - .mask = PMX_SSP_CS_MASK, - }, -}; - -struct pmx_dev spear310_pmx_fsmc = { - .name = "fsmc", - .modes = pmx_fsmc_modes, - .mode_count = ARRAY_SIZE(pmx_fsmc_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_rs485_0_1_modes[] = { - { - .ids = 0x00, - .mask = PMX_MII_MASK, - }, -}; - -struct pmx_dev spear310_pmx_rs485_0_1 = { - .name = "rs485_0_1", - .modes = pmx_rs485_0_1_modes, - .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_tdm0_modes[] = { - { - .ids = 0x00, - .mask = PMX_MII_MASK, - }, -}; - -struct pmx_dev spear310_pmx_tdm0 = { - .name = "tdm0", - .modes = pmx_tdm0_modes, - .mode_count = ARRAY_SIZE(pmx_tdm0_modes), - .enb_on_reset = 1, -}; +#include <mach/spear.h> + +#define SPEAR310_UART1_BASE UL(0xB2000000) +#define SPEAR310_UART2_BASE UL(0xB2080000) +#define SPEAR310_UART3_BASE UL(0xB2100000) +#define SPEAR310_UART4_BASE UL(0xB2180000) +#define SPEAR310_UART5_BASE UL(0xB2200000) +#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000) + +/* Interrupt registers offsets and masks */ +#define SPEAR310_INT_STS_MASK_REG 0x04 +#define SPEAR310_SMII0_IRQ_MASK (1 << 0) +#define SPEAR310_SMII1_IRQ_MASK (1 << 1) +#define SPEAR310_SMII2_IRQ_MASK (1 << 2) +#define SPEAR310_SMII3_IRQ_MASK (1 << 3) +#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4) +#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5) +#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6) +#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7) +#define SPEAR310_UART1_IRQ_MASK (1 << 8) +#define SPEAR310_UART2_IRQ_MASK (1 << 9) +#define SPEAR310_UART3_IRQ_MASK (1 << 10) +#define SPEAR310_UART4_IRQ_MASK (1 << 11) +#define SPEAR310_UART5_IRQ_MASK (1 << 12) +#define SPEAR310_EMI_IRQ_MASK (1 << 13) +#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14) +#define SPEAR310_RS485_0_IRQ_MASK (1 << 15) +#define SPEAR310_RS485_1_IRQ_MASK (1 << 16) + +#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF +#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00 +#define SPEAR310_SHIRQ_RAS3_MASK 0x02000 +#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000 + +/* SPEAr310 Virtual irq definitions */ +/* IRQs sharing IRQ_GEN_RAS_1 */ +#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0) +#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1) +#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2) +#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3) +#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4) +#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5) +#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6) +#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7) + +/* IRQs sharing IRQ_GEN_RAS_2 */ +#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8) +#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9) +#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10) +#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11) +#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12) + +/* IRQs sharing IRQ_GEN_RAS_3 */ +#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13) +#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14) + +/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ +#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15) +#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16) +#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17) -/* pmx driver structure */ -static struct pmx_driver pmx_driver = { - .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, -}; /* spear3xx shared irq */ static struct shirq_dev_config shirq_ras1_config[] = { @@ -255,17 +198,247 @@ static struct spear_shirq shirq_intrcomm_ras = { }, }; -/* Add spear310 specific devices here */ +/* DMAC platform data's slave info */ +struct pl08x_channel_data spear310_dma_info[] = { + { + .bus_id = "uart0_rx", + .min_signal = 2, + .max_signal = 2, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart0_tx", + .min_signal = 3, + .max_signal = 3, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ssp0_rx", + .min_signal = 8, + .max_signal = 8, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ssp0_tx", + .min_signal = 9, + .max_signal = 9, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "i2c_rx", + .min_signal = 10, + .max_signal = 10, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "i2c_tx", + .min_signal = 11, + .max_signal = 11, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "irda", + .min_signal = 12, + .max_signal = 12, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "adc", + .min_signal = 13, + .max_signal = 13, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "to_jpeg", + .min_signal = 14, + .max_signal = 14, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "from_jpeg", + .min_signal = 15, + .max_signal = 15, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart1_rx", + .min_signal = 0, + .max_signal = 0, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart1_tx", + .min_signal = 1, + .max_signal = 1, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart2_rx", + .min_signal = 2, + .max_signal = 2, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart2_tx", + .min_signal = 3, + .max_signal = 3, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart3_rx", + .min_signal = 4, + .max_signal = 4, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart3_tx", + .min_signal = 5, + .max_signal = 5, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart4_rx", + .min_signal = 6, + .max_signal = 6, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart4_tx", + .min_signal = 7, + .max_signal = 7, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart5_rx", + .min_signal = 8, + .max_signal = 8, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart5_tx", + .min_signal = 9, + .max_signal = 9, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras5_rx", + .min_signal = 10, + .max_signal = 10, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras5_tx", + .min_signal = 11, + .max_signal = 11, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras6_rx", + .min_signal = 12, + .max_signal = 12, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras6_tx", + .min_signal = 13, + .max_signal = 13, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras7_rx", + .min_signal = 14, + .max_signal = 14, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras7_tx", + .min_signal = 15, + .max_signal = 15, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, +}; -/* spear310 routines */ -void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, - u8 pmx_dev_count) +/* uart devices plat data */ +static struct amba_pl011_data spear310_uart_data[] = { + { + .dma_filter = pl08x_filter_id, + .dma_tx_param = "uart1_tx", + .dma_rx_param = "uart1_rx", + }, { + .dma_filter = pl08x_filter_id, + .dma_tx_param = "uart2_tx", + .dma_rx_param = "uart2_rx", + }, { + .dma_filter = pl08x_filter_id, + .dma_tx_param = "uart3_tx", + .dma_rx_param = "uart3_rx", + }, { + .dma_filter = pl08x_filter_id, + .dma_tx_param = "uart4_tx", + .dma_rx_param = "uart4_rx", + }, { + .dma_filter = pl08x_filter_id, + .dma_tx_param = "uart5_tx", + .dma_rx_param = "uart5_rx", + }, +}; + +/* Add SPEAr310 auxdata to pass platform data */ +static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, + &pl022_plat_data), + OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL, + &pl080_plat_data), + OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL, + &spear310_uart_data[0]), + OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL, + &spear310_uart_data[1]), + OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL, + &spear310_uart_data[2]), + OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL, + &spear310_uart_data[3]), + OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL, + &spear310_uart_data[4]), + {} +}; + +static void __init spear310_dt_init(void) { void __iomem *base; - int ret = 0; + int ret; - /* call spear3xx family common init function */ - spear3xx_init(); + pl080_plat_data.slave_channels = spear310_dma_info; + pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info); + + of_platform_populate(NULL, of_default_bus_match_table, + spear310_auxdata_lookup, NULL); /* shared irq registration */ base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K); @@ -274,35 +447,45 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, shirq_ras1.regs.base = base; ret = spear_shirq_register(&shirq_ras1); if (ret) - printk(KERN_ERR "Error registering Shared IRQ 1\n"); + pr_err("Error registering Shared IRQ 1\n"); /* shirq 2 */ shirq_ras2.regs.base = base; ret = spear_shirq_register(&shirq_ras2); if (ret) - printk(KERN_ERR "Error registering Shared IRQ 2\n"); + pr_err("Error registering Shared IRQ 2\n"); /* shirq 3 */ shirq_ras3.regs.base = base; ret = spear_shirq_register(&shirq_ras3); if (ret) - printk(KERN_ERR "Error registering Shared IRQ 3\n"); + pr_err("Error registering Shared IRQ 3\n"); /* shirq 4 */ shirq_intrcomm_ras.regs.base = base; ret = spear_shirq_register(&shirq_intrcomm_ras); if (ret) - printk(KERN_ERR "Error registering Shared IRQ 4\n"); + pr_err("Error registering Shared IRQ 4\n"); } +} - /* pmx initialization */ - pmx_driver.base = base; - pmx_driver.mode = pmx_mode; - pmx_driver.devs = pmx_devs; - pmx_driver.devs_count = pmx_dev_count; +static const char * const spear310_dt_board_compat[] = { + "st,spear310", + "st,spear310-evb", + NULL, +}; - ret = pmx_register(&pmx_driver); - if (ret) - printk(KERN_ERR "padmux: registration failed. err no: %d\n", - ret); +static void __init spear310_map_io(void) +{ + spear3xx_map_io(); } + +DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree") + .map_io = spear310_map_io, + .init_irq = spear3xx_dt_init_irq, + .handle_irq = vic_handle_irq, + .timer = &spear3xx_timer, + .init_machine = spear310_dt_init, + .restart = spear_restart, + .dt_compat = spear310_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c deleted file mode 100644 index f92c4993f65a..000000000000 --- a/arch/arm/mach-spear3xx/spear310_evb.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * arch/arm/mach-spear3xx/spear310_evb.c - * - * SPEAr310 evaluation board source file - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <asm/hardware/vic.h> -#include <asm/mach/arch.h> -#include <asm/mach-types.h> -#include <mach/generic.h> -#include <mach/hardware.h> - -/* padmux devices to enable */ -static struct pmx_dev *pmx_devs[] = { - /* spear3xx specific devices */ - &spear3xx_pmx_i2c, - &spear3xx_pmx_ssp, - &spear3xx_pmx_gpio_pin0, - &spear3xx_pmx_gpio_pin1, - &spear3xx_pmx_gpio_pin2, - &spear3xx_pmx_gpio_pin3, - &spear3xx_pmx_gpio_pin4, - &spear3xx_pmx_gpio_pin5, - &spear3xx_pmx_uart0, - - /* spear310 specific devices */ - &spear310_pmx_emi_cs_0_1_4_5, - &spear310_pmx_emi_cs_2_3, - &spear310_pmx_uart1, - &spear310_pmx_uart2, - &spear310_pmx_uart3_4_5, - &spear310_pmx_fsmc, - &spear310_pmx_rs485_0_1, - &spear310_pmx_tdm0, -}; - -static struct amba_device *amba_devs[] __initdata = { - /* spear3xx specific devices */ - &spear3xx_gpio_device, - &spear3xx_uart_device, - - /* spear310 specific devices */ -}; - -static struct platform_device *plat_devs[] __initdata = { - /* spear3xx specific devices */ - - /* spear310 specific devices */ -}; - -static void __init spear310_evb_init(void) -{ - unsigned int i; - - /* call spear310 machine init function */ - spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs)); - - /* Add Platform Devices */ - platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); - - /* Add Amba Devices */ - for (i = 0; i < ARRAY_SIZE(amba_devs); i++) - amba_device_register(amba_devs[i], &iomem_resource); -} - -MACHINE_START(SPEAR310, "ST-SPEAR310-EVB") - .atag_offset = 0x100, - .map_io = spear3xx_map_io, - .init_irq = spear3xx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &spear3xx_timer, - .init_machine = spear310_evb_init, - .restart = spear_restart, -MACHINE_END diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c index deaaf199612c..a88fa841d29d 100644 --- a/arch/arm/mach-spear3xx/spear320.c +++ b/arch/arm/mach-spear3xx/spear320.c @@ -3,386 +3,84 @@ * * SPEAr320 machine source file * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> + * Copyright (C) 2009-2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#include <linux/ptrace.h> -#include <asm/irq.h> +#define pr_fmt(fmt) "SPEAr320: " fmt + +#include <linux/amba/pl022.h> +#include <linux/amba/pl08x.h> +#include <linux/amba/serial.h> +#include <linux/of_platform.h> +#include <asm/hardware/vic.h> +#include <asm/mach/arch.h> #include <plat/shirq.h> #include <mach/generic.h> -#include <mach/hardware.h> - -/* pad multiplexing support */ -/* muxing registers */ -#define PAD_MUX_CONFIG_REG 0x0C -#define MODE_CONFIG_REG 0x10 - -/* modes */ -#define AUTO_NET_SMII_MODE (1 << 0) -#define AUTO_NET_MII_MODE (1 << 1) -#define AUTO_EXP_MODE (1 << 2) -#define SMALL_PRINTERS_MODE (1 << 3) -#define ALL_MODES 0xF - -struct pmx_mode spear320_auto_net_smii_mode = { - .id = AUTO_NET_SMII_MODE, - .name = "Automation Networking SMII Mode", - .mask = 0x00, -}; - -struct pmx_mode spear320_auto_net_mii_mode = { - .id = AUTO_NET_MII_MODE, - .name = "Automation Networking MII Mode", - .mask = 0x01, -}; - -struct pmx_mode spear320_auto_exp_mode = { - .id = AUTO_EXP_MODE, - .name = "Automation Expanded Mode", - .mask = 0x02, -}; - -struct pmx_mode spear320_small_printers_mode = { - .id = SMALL_PRINTERS_MODE, - .name = "Small Printers Mode", - .mask = 0x03, -}; - -/* devices */ -static struct pmx_dev_mode pmx_clcd_modes[] = { - { - .ids = AUTO_NET_SMII_MODE, - .mask = 0x0, - }, -}; - -struct pmx_dev spear320_pmx_clcd = { - .name = "clcd", - .modes = pmx_clcd_modes, - .mode_count = ARRAY_SIZE(pmx_clcd_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_emi_modes[] = { - { - .ids = AUTO_EXP_MODE, - .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, - }, -}; - -struct pmx_dev spear320_pmx_emi = { - .name = "emi", - .modes = pmx_emi_modes, - .mode_count = ARRAY_SIZE(pmx_emi_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_fsmc_modes[] = { - { - .ids = ALL_MODES, - .mask = 0x0, - }, -}; - -struct pmx_dev spear320_pmx_fsmc = { - .name = "fsmc", - .modes = pmx_fsmc_modes, - .mode_count = ARRAY_SIZE(pmx_fsmc_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_spp_modes[] = { - { - .ids = SMALL_PRINTERS_MODE, - .mask = 0x0, - }, -}; - -struct pmx_dev spear320_pmx_spp = { - .name = "spp", - .modes = pmx_spp_modes, - .mode_count = ARRAY_SIZE(pmx_spp_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_sdhci_modes[] = { - { - .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | - SMALL_PRINTERS_MODE, - .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, - }, -}; - -struct pmx_dev spear320_pmx_sdhci = { - .name = "sdhci", - .modes = pmx_sdhci_modes, - .mode_count = ARRAY_SIZE(pmx_sdhci_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_i2s_modes[] = { - { - .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, - .mask = PMX_UART0_MODEM_MASK, - }, -}; - -struct pmx_dev spear320_pmx_i2s = { - .name = "i2s", - .modes = pmx_i2s_modes, - .mode_count = ARRAY_SIZE(pmx_i2s_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_uart1_modes[] = { - { - .ids = ALL_MODES, - .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK, - }, -}; - -struct pmx_dev spear320_pmx_uart1 = { - .name = "uart1", - .modes = pmx_uart1_modes, - .mode_count = ARRAY_SIZE(pmx_uart1_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_uart1_modem_modes[] = { - { - .ids = AUTO_EXP_MODE, - .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | - PMX_SSP_CS_MASK, - }, { - .ids = SMALL_PRINTERS_MODE, - .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK | - PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK, - }, -}; - -struct pmx_dev spear320_pmx_uart1_modem = { - .name = "uart1_modem", - .modes = pmx_uart1_modem_modes, - .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_uart2_modes[] = { - { - .ids = ALL_MODES, - .mask = PMX_FIRDA_MASK, - }, -}; - -struct pmx_dev spear320_pmx_uart2 = { - .name = "uart2", - .modes = pmx_uart2_modes, - .mode_count = ARRAY_SIZE(pmx_uart2_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_touchscreen_modes[] = { - { - .ids = AUTO_NET_SMII_MODE, - .mask = PMX_SSP_CS_MASK, - }, -}; - -struct pmx_dev spear320_pmx_touchscreen = { - .name = "touchscreen", - .modes = pmx_touchscreen_modes, - .mode_count = ARRAY_SIZE(pmx_touchscreen_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_can_modes[] = { - { - .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE, - .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | - PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, - }, -}; - -struct pmx_dev spear320_pmx_can = { - .name = "can", - .modes = pmx_can_modes, - .mode_count = ARRAY_SIZE(pmx_can_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_sdhci_led_modes[] = { - { - .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, - .mask = PMX_SSP_CS_MASK, - }, -}; - -struct pmx_dev spear320_pmx_sdhci_led = { - .name = "sdhci_led", - .modes = pmx_sdhci_led_modes, - .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_pwm0_modes[] = { - { - .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, - .mask = PMX_UART0_MODEM_MASK, - }, { - .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE, - .mask = PMX_MII_MASK, - }, -}; - -struct pmx_dev spear320_pmx_pwm0 = { - .name = "pwm0", - .modes = pmx_pwm0_modes, - .mode_count = ARRAY_SIZE(pmx_pwm0_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_pwm1_modes[] = { - { - .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, - .mask = PMX_UART0_MODEM_MASK, - }, { - .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE, - .mask = PMX_MII_MASK, - }, -}; - -struct pmx_dev spear320_pmx_pwm1 = { - .name = "pwm1", - .modes = pmx_pwm1_modes, - .mode_count = ARRAY_SIZE(pmx_pwm1_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_pwm2_modes[] = { - { - .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, - .mask = PMX_SSP_CS_MASK, - }, { - .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE, - .mask = PMX_MII_MASK, - }, -}; - -struct pmx_dev spear320_pmx_pwm2 = { - .name = "pwm2", - .modes = pmx_pwm2_modes, - .mode_count = ARRAY_SIZE(pmx_pwm2_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_pwm3_modes[] = { - { - .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, - .mask = PMX_MII_MASK, - }, -}; - -struct pmx_dev spear320_pmx_pwm3 = { - .name = "pwm3", - .modes = pmx_pwm3_modes, - .mode_count = ARRAY_SIZE(pmx_pwm3_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_ssp1_modes[] = { - { - .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, - .mask = PMX_MII_MASK, - }, -}; - -struct pmx_dev spear320_pmx_ssp1 = { - .name = "ssp1", - .modes = pmx_ssp1_modes, - .mode_count = ARRAY_SIZE(pmx_ssp1_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_ssp2_modes[] = { - { - .ids = AUTO_NET_SMII_MODE, - .mask = PMX_MII_MASK, - }, -}; - -struct pmx_dev spear320_pmx_ssp2 = { - .name = "ssp2", - .modes = pmx_ssp2_modes, - .mode_count = ARRAY_SIZE(pmx_ssp2_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_mii1_modes[] = { - { - .ids = AUTO_NET_MII_MODE, - .mask = 0x0, - }, -}; - -struct pmx_dev spear320_pmx_mii1 = { - .name = "mii1", - .modes = pmx_mii1_modes, - .mode_count = ARRAY_SIZE(pmx_mii1_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_smii0_modes[] = { - { - .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE, - .mask = PMX_MII_MASK, - }, -}; - -struct pmx_dev spear320_pmx_smii0 = { - .name = "smii0", - .modes = pmx_smii0_modes, - .mode_count = ARRAY_SIZE(pmx_smii0_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_smii1_modes[] = { - { - .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE, - .mask = PMX_MII_MASK, - }, -}; - -struct pmx_dev spear320_pmx_smii1 = { - .name = "smii1", - .modes = pmx_smii1_modes, - .mode_count = ARRAY_SIZE(pmx_smii1_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_i2c1_modes[] = { - { - .ids = AUTO_EXP_MODE, - .mask = 0x0, - }, -}; - -struct pmx_dev spear320_pmx_i2c1 = { - .name = "i2c1", - .modes = pmx_i2c1_modes, - .mode_count = ARRAY_SIZE(pmx_i2c1_modes), - .enb_on_reset = 1, -}; - -/* pmx driver structure */ -static struct pmx_driver pmx_driver = { - .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007}, - .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, -}; +#include <mach/spear.h> + +#define SPEAR320_UART1_BASE UL(0xA3000000) +#define SPEAR320_UART2_BASE UL(0xA4000000) +#define SPEAR320_SSP0_BASE UL(0xA5000000) +#define SPEAR320_SSP1_BASE UL(0xA6000000) + +/* Interrupt registers offsets and masks */ +#define SPEAR320_INT_STS_MASK_REG 0x04 +#define SPEAR320_INT_CLR_MASK_REG 0x04 +#define SPEAR320_INT_ENB_MASK_REG 0x08 +#define SPEAR320_GPIO_IRQ_MASK (1 << 0) +#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1) +#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2) +#define SPEAR320_EMI_IRQ_MASK (1 << 7) +#define SPEAR320_CLCD_IRQ_MASK (1 << 8) +#define SPEAR320_SPP_IRQ_MASK (1 << 9) +#define SPEAR320_SDHCI_IRQ_MASK (1 << 10) +#define SPEAR320_CAN_U_IRQ_MASK (1 << 11) +#define SPEAR320_CAN_L_IRQ_MASK (1 << 12) +#define SPEAR320_UART1_IRQ_MASK (1 << 13) +#define SPEAR320_UART2_IRQ_MASK (1 << 14) +#define SPEAR320_SSP1_IRQ_MASK (1 << 15) +#define SPEAR320_SSP2_IRQ_MASK (1 << 16) +#define SPEAR320_SMII0_IRQ_MASK (1 << 17) +#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18) +#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19) +#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20) +#define SPEAR320_I2C1_IRQ_MASK (1 << 21) + +#define SPEAR320_SHIRQ_RAS1_MASK 0x000380 +#define SPEAR320_SHIRQ_RAS3_MASK 0x000007 +#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800 + +/* SPEAr320 Virtual irq definitions */ +/* IRQs sharing IRQ_GEN_RAS_1 */ +#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0) +#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1) +#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2) + +/* IRQs sharing IRQ_GEN_RAS_2 */ +#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2 + +/* IRQs sharing IRQ_GEN_RAS_3 */ +#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3) +#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4) +#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5) + +/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ +#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6) +#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7) +#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8) +#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9) +#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10) +#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11) +#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12) +#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13) +#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14) +#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15) +#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16) /* spear3xx shared irq */ static struct shirq_dev_config shirq_ras1_config[] = { @@ -508,17 +206,250 @@ static struct spear_shirq shirq_intrcomm_ras = { }, }; -/* Add spear320 specific devices here */ +/* DMAC platform data's slave info */ +struct pl08x_channel_data spear320_dma_info[] = { + { + .bus_id = "uart0_rx", + .min_signal = 2, + .max_signal = 2, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart0_tx", + .min_signal = 3, + .max_signal = 3, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ssp0_rx", + .min_signal = 8, + .max_signal = 8, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ssp0_tx", + .min_signal = 9, + .max_signal = 9, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "i2c0_rx", + .min_signal = 10, + .max_signal = 10, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "i2c0_tx", + .min_signal = 11, + .max_signal = 11, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "irda", + .min_signal = 12, + .max_signal = 12, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "adc", + .min_signal = 13, + .max_signal = 13, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "to_jpeg", + .min_signal = 14, + .max_signal = 14, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "from_jpeg", + .min_signal = 15, + .max_signal = 15, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ssp1_rx", + .min_signal = 0, + .max_signal = 0, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ssp1_tx", + .min_signal = 1, + .max_signal = 1, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ssp2_rx", + .min_signal = 2, + .max_signal = 2, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ssp2_tx", + .min_signal = 3, + .max_signal = 3, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "uart1_rx", + .min_signal = 4, + .max_signal = 4, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "uart1_tx", + .min_signal = 5, + .max_signal = 5, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "uart2_rx", + .min_signal = 6, + .max_signal = 6, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "uart2_tx", + .min_signal = 7, + .max_signal = 7, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "i2c1_rx", + .min_signal = 8, + .max_signal = 8, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "i2c1_tx", + .min_signal = 9, + .max_signal = 9, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "i2c2_rx", + .min_signal = 10, + .max_signal = 10, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "i2c2_tx", + .min_signal = 11, + .max_signal = 11, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "i2s_rx", + .min_signal = 12, + .max_signal = 12, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "i2s_tx", + .min_signal = 13, + .max_signal = 13, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "rs485_rx", + .min_signal = 14, + .max_signal = 14, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "rs485_tx", + .min_signal = 15, + .max_signal = 15, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, +}; + +static struct pl022_ssp_controller spear320_ssp_data[] = { + { + .bus_id = 1, + .enable_dma = 1, + .dma_filter = pl08x_filter_id, + .dma_tx_param = "ssp1_tx", + .dma_rx_param = "ssp1_rx", + .num_chipselect = 2, + }, { + .bus_id = 2, + .enable_dma = 1, + .dma_filter = pl08x_filter_id, + .dma_tx_param = "ssp2_tx", + .dma_rx_param = "ssp2_rx", + .num_chipselect = 2, + } +}; + +static struct amba_pl011_data spear320_uart_data[] = { + { + .dma_filter = pl08x_filter_id, + .dma_tx_param = "uart1_tx", + .dma_rx_param = "uart1_rx", + }, { + .dma_filter = pl08x_filter_id, + .dma_tx_param = "uart2_tx", + .dma_rx_param = "uart2_rx", + }, +}; -/* spear320 routines */ -void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, - u8 pmx_dev_count) +/* Add SPEAr310 auxdata to pass platform data */ +static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, + &pl022_plat_data), + OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL, + &pl080_plat_data), + OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL, + &spear320_ssp_data[0]), + OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL, + &spear320_ssp_data[1]), + OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL, + &spear320_uart_data[0]), + OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL, + &spear320_uart_data[1]), + {} +}; + +static void __init spear320_dt_init(void) { void __iomem *base; - int ret = 0; + int ret; - /* call spear3xx family common init function */ - spear3xx_init(); + pl080_plat_data.slave_channels = spear320_dma_info; + pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info); + + of_platform_populate(NULL, of_default_bus_match_table, + spear320_auxdata_lookup, NULL); /* shared irq registration */ base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K); @@ -527,29 +458,49 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, shirq_ras1.regs.base = base; ret = spear_shirq_register(&shirq_ras1); if (ret) - printk(KERN_ERR "Error registering Shared IRQ 1\n"); + pr_err("Error registering Shared IRQ 1\n"); /* shirq 3 */ shirq_ras3.regs.base = base; ret = spear_shirq_register(&shirq_ras3); if (ret) - printk(KERN_ERR "Error registering Shared IRQ 3\n"); + pr_err("Error registering Shared IRQ 3\n"); /* shirq 4 */ shirq_intrcomm_ras.regs.base = base; ret = spear_shirq_register(&shirq_intrcomm_ras); if (ret) - printk(KERN_ERR "Error registering Shared IRQ 4\n"); + pr_err("Error registering Shared IRQ 4\n"); } +} + +static const char * const spear320_dt_board_compat[] = { + "st,spear320", + "st,spear320-evb", + NULL, +}; - /* pmx initialization */ - pmx_driver.base = base; - pmx_driver.mode = pmx_mode; - pmx_driver.devs = pmx_devs; - pmx_driver.devs_count = pmx_dev_count; +struct map_desc spear320_io_desc[] __initdata = { + { + .virtual = VA_SPEAR320_SOC_CONFIG_BASE, + .pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE), + .length = SZ_16M, + .type = MT_DEVICE + }, +}; - ret = pmx_register(&pmx_driver); - if (ret) - printk(KERN_ERR "padmux: registration failed. err no: %d\n", - ret); +static void __init spear320_map_io(void) +{ + iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc)); + spear3xx_map_io(); } + +DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree") + .map_io = spear320_map_io, + .init_irq = spear3xx_dt_init_irq, + .handle_irq = vic_handle_irq, + .timer = &spear3xx_timer, + .init_machine = spear320_dt_init, + .restart = spear_restart, + .dt_compat = spear320_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c deleted file mode 100644 index 105334ab7021..000000000000 --- a/arch/arm/mach-spear3xx/spear320_evb.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * arch/arm/mach-spear3xx/spear320_evb.c - * - * SPEAr320 evaluation board source file - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <asm/hardware/vic.h> -#include <asm/mach/arch.h> -#include <asm/mach-types.h> -#include <mach/generic.h> -#include <mach/hardware.h> - -/* padmux devices to enable */ -static struct pmx_dev *pmx_devs[] = { - /* spear3xx specific devices */ - &spear3xx_pmx_i2c, - &spear3xx_pmx_ssp, - &spear3xx_pmx_mii, - &spear3xx_pmx_uart0, - - /* spear320 specific devices */ - &spear320_pmx_fsmc, - &spear320_pmx_sdhci, - &spear320_pmx_i2s, - &spear320_pmx_uart1, - &spear320_pmx_uart2, - &spear320_pmx_can, - &spear320_pmx_pwm0, - &spear320_pmx_pwm1, - &spear320_pmx_pwm2, - &spear320_pmx_mii1, -}; - -static struct amba_device *amba_devs[] __initdata = { - /* spear3xx specific devices */ - &spear3xx_gpio_device, - &spear3xx_uart_device, - - /* spear320 specific devices */ -}; - -static struct platform_device *plat_devs[] __initdata = { - /* spear3xx specific devices */ - - /* spear320 specific devices */ -}; - -static void __init spear320_evb_init(void) -{ - unsigned int i; - - /* call spear320 machine init function */ - spear320_init(&spear320_auto_net_mii_mode, pmx_devs, - ARRAY_SIZE(pmx_devs)); - - /* Add Platform Devices */ - platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); - - /* Add Amba Devices */ - for (i = 0; i < ARRAY_SIZE(amba_devs); i++) - amba_device_register(amba_devs[i], &iomem_resource); -} - -MACHINE_START(SPEAR320, "ST-SPEAR320-EVB") - .atag_offset = 0x100, - .map_io = spear3xx_map_io, - .init_irq = spear3xx_init_irq, - .handle_irq = vic_handle_irq, - .timer = &spear3xx_timer, - .init_machine = spear320_evb_init, - .restart = spear_restart, -MACHINE_END diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c index b1733c37f209..f22419ed74a8 100644 --- a/arch/arm/mach-spear3xx/spear3xx.c +++ b/arch/arm/mach-spear3xx/spear3xx.c @@ -3,71 +3,78 @@ * * SPEAr3XX machines common source file * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> + * Copyright (C) 2009-2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#include <linux/types.h> -#include <linux/amba/pl061.h> -#include <linux/ptrace.h> +#define pr_fmt(fmt) "SPEAr3xx: " fmt + +#include <linux/amba/pl022.h> +#include <linux/amba/pl08x.h> +#include <linux/of_irq.h> #include <linux/io.h> +#include <asm/hardware/pl080.h> #include <asm/hardware/vic.h> -#include <asm/irq.h> -#include <asm/mach/arch.h> +#include <plat/pl080.h> #include <mach/generic.h> -#include <mach/hardware.h> - -/* Add spear3xx machines common devices here */ -/* gpio device registration */ -static struct pl061_platform_data gpio_plat_data = { - .gpio_base = 0, - .irq_base = SPEAR3XX_GPIO_INT_BASE, +#include <mach/spear.h> + +/* ssp device registration */ +struct pl022_ssp_controller pl022_plat_data = { + .bus_id = 0, + .enable_dma = 1, + .dma_filter = pl08x_filter_id, + .dma_tx_param = "ssp0_tx", + .dma_rx_param = "ssp0_rx", + /* + * This is number of spi devices that can be connected to spi. There are + * two type of chipselects on which slave devices can work. One is chip + * select provided by spi masters other is controlled through external + * gpio's. We can't use chipselect provided from spi master (because as + * soon as FIFO becomes empty, CS is disabled and transfer ends). So + * this number now depends on number of gpios available for spi. each + * slave on each master requires a separate gpio pin. + */ + .num_chipselect = 2, +}; + +/* dmac device registration */ +struct pl08x_platform_data pl080_plat_data = { + .memcpy_channel = { + .bus_id = "memcpy", + .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \ + PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \ + PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \ + PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \ + PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \ + PL080_CONTROL_PROT_SYS), + }, + .lli_buses = PL08X_AHB1, + .mem_buses = PL08X_AHB1, + .get_signal = pl080_get_signal, + .put_signal = pl080_put_signal, }; -AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE, - {SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data); - -/* uart device registration */ -AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE, - {SPEAR3XX_IRQ_UART}, NULL); - -/* Do spear3xx familiy common initialization part here */ -void __init spear3xx_init(void) -{ - /* nothing to do for now */ -} - -/* This will initialize vic */ -void __init spear3xx_init_irq(void) -{ - vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0); -} - -/* Following will create static virtual/physical mappings */ +/* + * Following will create 16MB static virtual/physical mappings + * PHYSICAL VIRTUAL + * 0xD0000000 0xFD000000 + * 0xFC000000 0xFC000000 + */ struct map_desc spear3xx_io_desc[] __initdata = { { - .virtual = VA_SPEAR3XX_ICM1_UART_BASE, - .pfn = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE), - .length = SZ_4K, - .type = MT_DEVICE - }, { - .virtual = VA_SPEAR3XX_ML1_VIC_BASE, - .pfn = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE), - .length = SZ_4K, - .type = MT_DEVICE - }, { - .virtual = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE, - .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE), - .length = SZ_4K, + .virtual = VA_SPEAR3XX_ICM1_2_BASE, + .pfn = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE), + .length = SZ_16M, .type = MT_DEVICE }, { - .virtual = VA_SPEAR3XX_ICM3_MISC_REG_BASE, - .pfn = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE), - .length = SZ_4K, + .virtual = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE, + .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE), + .length = SZ_16M, .type = MT_DEVICE }, }; @@ -76,441 +83,15 @@ struct map_desc spear3xx_io_desc[] __initdata = { void __init spear3xx_map_io(void) { iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); - - /* This will initialize clock framework */ - spear3xx_clk_init(); } -/* pad multiplexing support */ -/* devices */ -static struct pmx_dev_mode pmx_firda_modes[] = { - { - .ids = 0xffffffff, - .mask = PMX_FIRDA_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_firda = { - .name = "firda", - .modes = pmx_firda_modes, - .mode_count = ARRAY_SIZE(pmx_firda_modes), - .enb_on_reset = 0, -}; - -static struct pmx_dev_mode pmx_i2c_modes[] = { - { - .ids = 0xffffffff, - .mask = PMX_I2C_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_i2c = { - .name = "i2c", - .modes = pmx_i2c_modes, - .mode_count = ARRAY_SIZE(pmx_i2c_modes), - .enb_on_reset = 0, -}; - -static struct pmx_dev_mode pmx_ssp_cs_modes[] = { - { - .ids = 0xffffffff, - .mask = PMX_SSP_CS_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_ssp_cs = { - .name = "ssp_chip_selects", - .modes = pmx_ssp_cs_modes, - .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes), - .enb_on_reset = 0, -}; - -static struct pmx_dev_mode pmx_ssp_modes[] = { - { - .ids = 0xffffffff, - .mask = PMX_SSP_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_ssp = { - .name = "ssp", - .modes = pmx_ssp_modes, - .mode_count = ARRAY_SIZE(pmx_ssp_modes), - .enb_on_reset = 0, -}; - -static struct pmx_dev_mode pmx_mii_modes[] = { - { - .ids = 0xffffffff, - .mask = PMX_MII_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_mii = { - .name = "mii", - .modes = pmx_mii_modes, - .mode_count = ARRAY_SIZE(pmx_mii_modes), - .enb_on_reset = 0, -}; - -static struct pmx_dev_mode pmx_gpio_pin0_modes[] = { - { - .ids = 0xffffffff, - .mask = PMX_GPIO_PIN0_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_gpio_pin0 = { - .name = "gpio_pin0", - .modes = pmx_gpio_pin0_modes, - .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes), - .enb_on_reset = 0, -}; - -static struct pmx_dev_mode pmx_gpio_pin1_modes[] = { - { - .ids = 0xffffffff, - .mask = PMX_GPIO_PIN1_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_gpio_pin1 = { - .name = "gpio_pin1", - .modes = pmx_gpio_pin1_modes, - .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes), - .enb_on_reset = 0, -}; - -static struct pmx_dev_mode pmx_gpio_pin2_modes[] = { - { - .ids = 0xffffffff, - .mask = PMX_GPIO_PIN2_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_gpio_pin2 = { - .name = "gpio_pin2", - .modes = pmx_gpio_pin2_modes, - .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes), - .enb_on_reset = 0, -}; - -static struct pmx_dev_mode pmx_gpio_pin3_modes[] = { - { - .ids = 0xffffffff, - .mask = PMX_GPIO_PIN3_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_gpio_pin3 = { - .name = "gpio_pin3", - .modes = pmx_gpio_pin3_modes, - .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes), - .enb_on_reset = 0, -}; - -static struct pmx_dev_mode pmx_gpio_pin4_modes[] = { - { - .ids = 0xffffffff, - .mask = PMX_GPIO_PIN4_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_gpio_pin4 = { - .name = "gpio_pin4", - .modes = pmx_gpio_pin4_modes, - .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes), - .enb_on_reset = 0, -}; - -static struct pmx_dev_mode pmx_gpio_pin5_modes[] = { - { - .ids = 0xffffffff, - .mask = PMX_GPIO_PIN5_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_gpio_pin5 = { - .name = "gpio_pin5", - .modes = pmx_gpio_pin5_modes, - .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes), - .enb_on_reset = 0, -}; - -static struct pmx_dev_mode pmx_uart0_modem_modes[] = { - { - .ids = 0xffffffff, - .mask = PMX_UART0_MODEM_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_uart0_modem = { - .name = "uart0_modem", - .modes = pmx_uart0_modem_modes, - .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes), - .enb_on_reset = 0, -}; - -static struct pmx_dev_mode pmx_uart0_modes[] = { - { - .ids = 0xffffffff, - .mask = PMX_UART0_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_uart0 = { - .name = "uart0", - .modes = pmx_uart0_modes, - .mode_count = ARRAY_SIZE(pmx_uart0_modes), - .enb_on_reset = 0, -}; - -static struct pmx_dev_mode pmx_timer_3_4_modes[] = { - { - .ids = 0xffffffff, - .mask = PMX_TIMER_3_4_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_timer_3_4 = { - .name = "timer_3_4", - .modes = pmx_timer_3_4_modes, - .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes), - .enb_on_reset = 0, -}; - -static struct pmx_dev_mode pmx_timer_1_2_modes[] = { - { - .ids = 0xffffffff, - .mask = PMX_TIMER_1_2_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_timer_1_2 = { - .name = "timer_1_2", - .modes = pmx_timer_1_2_modes, - .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes), - .enb_on_reset = 0, -}; - -#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) -/* plgpios devices */ -static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = { - { - .ids = 0x00, - .mask = PMX_FIRDA_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_plgpio_0_1 = { - .name = "plgpio 0 and 1", - .modes = pmx_plgpio_0_1_modes, - .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = { - { - .ids = 0x00, - .mask = PMX_UART0_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_plgpio_2_3 = { - .name = "plgpio 2 and 3", - .modes = pmx_plgpio_2_3_modes, - .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = { - { - .ids = 0x00, - .mask = PMX_I2C_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_plgpio_4_5 = { - .name = "plgpio 4 and 5", - .modes = pmx_plgpio_4_5_modes, - .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = { - { - .ids = 0x00, - .mask = PMX_SSP_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_plgpio_6_9 = { - .name = "plgpio 6 to 9", - .modes = pmx_plgpio_6_9_modes, - .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = { - { - .ids = 0x00, - .mask = PMX_MII_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_plgpio_10_27 = { - .name = "plgpio 10 to 27", - .modes = pmx_plgpio_10_27_modes, - .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_plgpio_28_modes[] = { - { - .ids = 0x00, - .mask = PMX_GPIO_PIN0_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_plgpio_28 = { - .name = "plgpio 28", - .modes = pmx_plgpio_28_modes, - .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_plgpio_29_modes[] = { - { - .ids = 0x00, - .mask = PMX_GPIO_PIN1_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_plgpio_29 = { - .name = "plgpio 29", - .modes = pmx_plgpio_29_modes, - .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_plgpio_30_modes[] = { - { - .ids = 0x00, - .mask = PMX_GPIO_PIN2_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_plgpio_30 = { - .name = "plgpio 30", - .modes = pmx_plgpio_30_modes, - .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_plgpio_31_modes[] = { - { - .ids = 0x00, - .mask = PMX_GPIO_PIN3_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_plgpio_31 = { - .name = "plgpio 31", - .modes = pmx_plgpio_31_modes, - .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_plgpio_32_modes[] = { - { - .ids = 0x00, - .mask = PMX_GPIO_PIN4_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_plgpio_32 = { - .name = "plgpio 32", - .modes = pmx_plgpio_32_modes, - .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_plgpio_33_modes[] = { - { - .ids = 0x00, - .mask = PMX_GPIO_PIN5_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_plgpio_33 = { - .name = "plgpio 33", - .modes = pmx_plgpio_33_modes, - .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = { - { - .ids = 0x00, - .mask = PMX_SSP_CS_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_plgpio_34_36 = { - .name = "plgpio 34 to 36", - .modes = pmx_plgpio_34_36_modes, - .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = { - { - .ids = 0x00, - .mask = PMX_UART0_MODEM_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_plgpio_37_42 = { - .name = "plgpio 37 to 42", - .modes = pmx_plgpio_37_42_modes, - .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = { - { - .ids = 0x00, - .mask = PMX_TIMER_1_2_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = { - .name = "plgpio 43, 44, 47 and 48", - .modes = pmx_plgpio_43_44_47_48_modes, - .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes), - .enb_on_reset = 1, -}; - -static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = { - { - .ids = 0x00, - .mask = PMX_TIMER_3_4_MASK, - }, -}; - -struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = { - .name = "plgpio 45, 46, 49 and 50", - .modes = pmx_plgpio_45_46_49_50_modes, - .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes), - .enb_on_reset = 1, -}; -#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */ - static void __init spear3xx_timer_init(void) { char pclk_name[] = "pll3_48m_clk"; struct clk *gpt_clk, *pclk; + spear3xx_clk_init(); + /* get the system timer clock */ gpt_clk = clk_get_sys("gpt0", NULL); if (IS_ERR(gpt_clk)) { @@ -530,9 +111,19 @@ static void __init spear3xx_timer_init(void) clk_put(gpt_clk); clk_put(pclk); - spear_setup_timer(); + spear_setup_of_timer(); } struct sys_timer spear3xx_timer = { .init = spear3xx_timer_init, }; + +static const struct of_device_id vic_of_match[] __initconst = { + { .compatible = "arm,pl190-vic", .data = vic_of_init, }, + { /* Sentinel */ } +}; + +void __init spear3xx_dt_init_irq(void) +{ + of_irq_init(vic_of_match); +} diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile index 76e5750552fc..898831d93f37 100644 --- a/arch/arm/mach-spear6xx/Makefile +++ b/arch/arm/mach-spear6xx/Makefile @@ -3,4 +3,4 @@ # # common files -obj-y += clock.o spear6xx.o +obj-y += spear6xx.o diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot index 4674a4c221db..af493da37ab6 100644 --- a/arch/arm/mach-spear6xx/Makefile.boot +++ b/arch/arm/mach-spear6xx/Makefile.boot @@ -1,3 +1,5 @@ zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 + +dtb-$(CONFIG_BOARD_SPEAR600_DT) += spear600-evb.dtb diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c deleted file mode 100644 index a86499a8a15f..000000000000 --- a/arch/arm/mach-spear6xx/clock.c +++ /dev/null @@ -1,683 +0,0 @@ -/* - * arch/arm/mach-spear6xx/clock.c - * - * SPEAr6xx machines clock framework source file - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/init.h> -#include <linux/io.h> -#include <linux/kernel.h> -#include <plat/clock.h> -#include <mach/misc_regs.h> - -/* root clks */ -/* 32 KHz oscillator clock */ -static struct clk osc_32k_clk = { - .flags = ALWAYS_ENABLED, - .rate = 32000, -}; - -/* 30 MHz oscillator clock */ -static struct clk osc_30m_clk = { - .flags = ALWAYS_ENABLED, - .rate = 30000000, -}; - -/* clock derived from 32 KHz osc clk */ -/* rtc clock */ -static struct clk rtc_clk = { - .pclk = &osc_32k_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = RTC_CLK_ENB, - .recalc = &follow_parent, -}; - -/* clock derived from 30 MHz osc clk */ -/* pll masks structure */ -static struct pll_clk_masks pll1_masks = { - .mode_mask = PLL_MODE_MASK, - .mode_shift = PLL_MODE_SHIFT, - .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK, - .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT, - .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK, - .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT, - .div_p_mask = PLL_DIV_P_MASK, - .div_p_shift = PLL_DIV_P_SHIFT, - .div_n_mask = PLL_DIV_N_MASK, - .div_n_shift = PLL_DIV_N_SHIFT, -}; - -/* pll1 configuration structure */ -static struct pll_clk_config pll1_config = { - .mode_reg = PLL1_CTR, - .cfg_reg = PLL1_FRQ, - .masks = &pll1_masks, -}; - -/* pll rate configuration table, in ascending order of rates */ -struct pll_rate_tbl pll_rtbl[] = { - {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */ - {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */ -}; - -/* PLL1 clock */ -static struct clk pll1_clk = { - .flags = ENABLED_ON_INIT, - .pclk = &osc_30m_clk, - .en_reg = PLL1_CTR, - .en_reg_bit = PLL_ENABLE, - .calc_rate = &pll_calc_rate, - .recalc = &pll_clk_recalc, - .set_rate = &pll_clk_set_rate, - .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1}, - .private_data = &pll1_config, -}; - -/* PLL3 48 MHz clock */ -static struct clk pll3_48m_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &osc_30m_clk, - .rate = 48000000, -}; - -/* watch dog timer clock */ -static struct clk wdt_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &osc_30m_clk, - .recalc = &follow_parent, -}; - -/* clock derived from pll1 clk */ -/* cpu clock */ -static struct clk cpu_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &pll1_clk, - .recalc = &follow_parent, -}; - -/* ahb masks structure */ -static struct bus_clk_masks ahb_masks = { - .mask = PLL_HCLK_RATIO_MASK, - .shift = PLL_HCLK_RATIO_SHIFT, -}; - -/* ahb configuration structure */ -static struct bus_clk_config ahb_config = { - .reg = CORE_CLK_CFG, - .masks = &ahb_masks, -}; - -/* ahb rate configuration table, in ascending order of rates */ -struct bus_rate_tbl bus_rtbl[] = { - {.div = 3}, /* == parent divided by 4 */ - {.div = 2}, /* == parent divided by 3 */ - {.div = 1}, /* == parent divided by 2 */ - {.div = 0}, /* == parent divided by 1 */ -}; - -/* ahb clock */ -static struct clk ahb_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &pll1_clk, - .calc_rate = &bus_calc_rate, - .recalc = &bus_clk_recalc, - .set_rate = &bus_clk_set_rate, - .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2}, - .private_data = &ahb_config, -}; - -/* auxiliary synthesizers masks */ -static struct aux_clk_masks aux_masks = { - .eq_sel_mask = AUX_EQ_SEL_MASK, - .eq_sel_shift = AUX_EQ_SEL_SHIFT, - .eq1_mask = AUX_EQ1_SEL, - .eq2_mask = AUX_EQ2_SEL, - .xscale_sel_mask = AUX_XSCALE_MASK, - .xscale_sel_shift = AUX_XSCALE_SHIFT, - .yscale_sel_mask = AUX_YSCALE_MASK, - .yscale_sel_shift = AUX_YSCALE_SHIFT, -}; - -/* uart configurations */ -static struct aux_clk_config uart_synth_config = { - .synth_reg = UART_CLK_SYNT, - .masks = &aux_masks, -}; - -/* aux rate configuration table, in ascending order of rates */ -struct aux_rate_tbl aux_rtbl[] = { - /* For PLL1 = 332 MHz */ - {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */ - {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */ - {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */ -}; - -/* uart synth clock */ -static struct clk uart_synth_clk = { - .en_reg = UART_CLK_SYNT, - .en_reg_bit = AUX_SYNT_ENB, - .pclk = &pll1_clk, - .calc_rate = &aux_calc_rate, - .recalc = &aux_clk_recalc, - .set_rate = &aux_clk_set_rate, - .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2}, - .private_data = &uart_synth_config, -}; - -/* uart parents */ -static struct pclk_info uart_pclk_info[] = { - { - .pclk = &uart_synth_clk, - .pclk_val = AUX_CLK_PLL1_VAL, - }, { - .pclk = &pll3_48m_clk, - .pclk_val = AUX_CLK_PLL3_VAL, - }, -}; - -/* uart parent select structure */ -static struct pclk_sel uart_pclk_sel = { - .pclk_info = uart_pclk_info, - .pclk_count = ARRAY_SIZE(uart_pclk_info), - .pclk_sel_reg = PERIP_CLK_CFG, - .pclk_sel_mask = UART_CLK_MASK, -}; - -/* uart0 clock */ -static struct clk uart0_clk = { - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = UART0_CLK_ENB, - .pclk_sel = &uart_pclk_sel, - .pclk_sel_shift = UART_CLK_SHIFT, - .recalc = &follow_parent, -}; - -/* uart1 clock */ -static struct clk uart1_clk = { - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = UART1_CLK_ENB, - .pclk_sel = &uart_pclk_sel, - .pclk_sel_shift = UART_CLK_SHIFT, - .recalc = &follow_parent, -}; - -/* firda configurations */ -static struct aux_clk_config firda_synth_config = { - .synth_reg = FIRDA_CLK_SYNT, - .masks = &aux_masks, -}; - -/* firda synth clock */ -static struct clk firda_synth_clk = { - .en_reg = FIRDA_CLK_SYNT, - .en_reg_bit = AUX_SYNT_ENB, - .pclk = &pll1_clk, - .calc_rate = &aux_calc_rate, - .recalc = &aux_clk_recalc, - .set_rate = &aux_clk_set_rate, - .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2}, - .private_data = &firda_synth_config, -}; - -/* firda parents */ -static struct pclk_info firda_pclk_info[] = { - { - .pclk = &firda_synth_clk, - .pclk_val = AUX_CLK_PLL1_VAL, - }, { - .pclk = &pll3_48m_clk, - .pclk_val = AUX_CLK_PLL3_VAL, - }, -}; - -/* firda parent select structure */ -static struct pclk_sel firda_pclk_sel = { - .pclk_info = firda_pclk_info, - .pclk_count = ARRAY_SIZE(firda_pclk_info), - .pclk_sel_reg = PERIP_CLK_CFG, - .pclk_sel_mask = FIRDA_CLK_MASK, -}; - -/* firda clock */ -static struct clk firda_clk = { - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = FIRDA_CLK_ENB, - .pclk_sel = &firda_pclk_sel, - .pclk_sel_shift = FIRDA_CLK_SHIFT, - .recalc = &follow_parent, -}; - -/* clcd configurations */ -static struct aux_clk_config clcd_synth_config = { - .synth_reg = CLCD_CLK_SYNT, - .masks = &aux_masks, -}; - -/* firda synth clock */ -static struct clk clcd_synth_clk = { - .en_reg = CLCD_CLK_SYNT, - .en_reg_bit = AUX_SYNT_ENB, - .pclk = &pll1_clk, - .calc_rate = &aux_calc_rate, - .recalc = &aux_clk_recalc, - .set_rate = &aux_clk_set_rate, - .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2}, - .private_data = &clcd_synth_config, -}; - -/* clcd parents */ -static struct pclk_info clcd_pclk_info[] = { - { - .pclk = &clcd_synth_clk, - .pclk_val = AUX_CLK_PLL1_VAL, - }, { - .pclk = &pll3_48m_clk, - .pclk_val = AUX_CLK_PLL3_VAL, - }, -}; - -/* clcd parent select structure */ -static struct pclk_sel clcd_pclk_sel = { - .pclk_info = clcd_pclk_info, - .pclk_count = ARRAY_SIZE(clcd_pclk_info), - .pclk_sel_reg = PERIP_CLK_CFG, - .pclk_sel_mask = CLCD_CLK_MASK, -}; - -/* clcd clock */ -static struct clk clcd_clk = { - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = CLCD_CLK_ENB, - .pclk_sel = &clcd_pclk_sel, - .pclk_sel_shift = CLCD_CLK_SHIFT, - .recalc = &follow_parent, -}; - -/* gpt synthesizer masks */ -static struct gpt_clk_masks gpt_masks = { - .mscale_sel_mask = GPT_MSCALE_MASK, - .mscale_sel_shift = GPT_MSCALE_SHIFT, - .nscale_sel_mask = GPT_NSCALE_MASK, - .nscale_sel_shift = GPT_NSCALE_SHIFT, -}; - -/* gpt rate configuration table, in ascending order of rates */ -struct gpt_rate_tbl gpt_rtbl[] = { - /* For pll1 = 332 MHz */ - {.mscale = 4, .nscale = 0}, /* 41.5 MHz */ - {.mscale = 2, .nscale = 0}, /* 55.3 MHz */ - {.mscale = 1, .nscale = 0}, /* 83 MHz */ -}; - -/* gpt0 synth clk config*/ -static struct gpt_clk_config gpt0_synth_config = { - .synth_reg = PRSC1_CLK_CFG, - .masks = &gpt_masks, -}; - -/* gpt synth clock */ -static struct clk gpt0_synth_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &pll1_clk, - .calc_rate = &gpt_calc_rate, - .recalc = &gpt_clk_recalc, - .set_rate = &gpt_clk_set_rate, - .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2}, - .private_data = &gpt0_synth_config, -}; - -/* gpt parents */ -static struct pclk_info gpt0_pclk_info[] = { - { - .pclk = &gpt0_synth_clk, - .pclk_val = AUX_CLK_PLL1_VAL, - }, { - .pclk = &pll3_48m_clk, - .pclk_val = AUX_CLK_PLL3_VAL, - }, -}; - -/* gpt parent select structure */ -static struct pclk_sel gpt0_pclk_sel = { - .pclk_info = gpt0_pclk_info, - .pclk_count = ARRAY_SIZE(gpt0_pclk_info), - .pclk_sel_reg = PERIP_CLK_CFG, - .pclk_sel_mask = GPT_CLK_MASK, -}; - -/* gpt0 ARM1 subsystem timer clock */ -static struct clk gpt0_clk = { - .flags = ALWAYS_ENABLED, - .pclk_sel = &gpt0_pclk_sel, - .pclk_sel_shift = GPT0_CLK_SHIFT, - .recalc = &follow_parent, -}; - - -/* Note: gpt0 and gpt1 share same parent clocks */ -/* gpt parent select structure */ -static struct pclk_sel gpt1_pclk_sel = { - .pclk_info = gpt0_pclk_info, - .pclk_count = ARRAY_SIZE(gpt0_pclk_info), - .pclk_sel_reg = PERIP_CLK_CFG, - .pclk_sel_mask = GPT_CLK_MASK, -}; - -/* gpt1 timer clock */ -static struct clk gpt1_clk = { - .flags = ALWAYS_ENABLED, - .pclk_sel = &gpt1_pclk_sel, - .pclk_sel_shift = GPT1_CLK_SHIFT, - .recalc = &follow_parent, -}; - -/* gpt2 synth clk config*/ -static struct gpt_clk_config gpt2_synth_config = { - .synth_reg = PRSC2_CLK_CFG, - .masks = &gpt_masks, -}; - -/* gpt synth clock */ -static struct clk gpt2_synth_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &pll1_clk, - .calc_rate = &gpt_calc_rate, - .recalc = &gpt_clk_recalc, - .set_rate = &gpt_clk_set_rate, - .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2}, - .private_data = &gpt2_synth_config, -}; - -/* gpt parents */ -static struct pclk_info gpt2_pclk_info[] = { - { - .pclk = &gpt2_synth_clk, - .pclk_val = AUX_CLK_PLL1_VAL, - }, { - .pclk = &pll3_48m_clk, - .pclk_val = AUX_CLK_PLL3_VAL, - }, -}; - -/* gpt parent select structure */ -static struct pclk_sel gpt2_pclk_sel = { - .pclk_info = gpt2_pclk_info, - .pclk_count = ARRAY_SIZE(gpt2_pclk_info), - .pclk_sel_reg = PERIP_CLK_CFG, - .pclk_sel_mask = GPT_CLK_MASK, -}; - -/* gpt2 timer clock */ -static struct clk gpt2_clk = { - .flags = ALWAYS_ENABLED, - .pclk_sel = &gpt2_pclk_sel, - .pclk_sel_shift = GPT2_CLK_SHIFT, - .recalc = &follow_parent, -}; - -/* gpt3 synth clk config*/ -static struct gpt_clk_config gpt3_synth_config = { - .synth_reg = PRSC3_CLK_CFG, - .masks = &gpt_masks, -}; - -/* gpt synth clock */ -static struct clk gpt3_synth_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &pll1_clk, - .calc_rate = &gpt_calc_rate, - .recalc = &gpt_clk_recalc, - .set_rate = &gpt_clk_set_rate, - .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2}, - .private_data = &gpt3_synth_config, -}; - -/* gpt parents */ -static struct pclk_info gpt3_pclk_info[] = { - { - .pclk = &gpt3_synth_clk, - .pclk_val = AUX_CLK_PLL1_VAL, - }, { - .pclk = &pll3_48m_clk, - .pclk_val = AUX_CLK_PLL3_VAL, - }, -}; - -/* gpt parent select structure */ -static struct pclk_sel gpt3_pclk_sel = { - .pclk_info = gpt3_pclk_info, - .pclk_count = ARRAY_SIZE(gpt3_pclk_info), - .pclk_sel_reg = PERIP_CLK_CFG, - .pclk_sel_mask = GPT_CLK_MASK, -}; - -/* gpt3 timer clock */ -static struct clk gpt3_clk = { - .flags = ALWAYS_ENABLED, - .pclk_sel = &gpt3_pclk_sel, - .pclk_sel_shift = GPT3_CLK_SHIFT, - .recalc = &follow_parent, -}; - -/* clock derived from pll3 clk */ -/* usbh0 clock */ -static struct clk usbh0_clk = { - .pclk = &pll3_48m_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = USBH0_CLK_ENB, - .recalc = &follow_parent, -}; - -/* usbh1 clock */ -static struct clk usbh1_clk = { - .pclk = &pll3_48m_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = USBH1_CLK_ENB, - .recalc = &follow_parent, -}; - -/* usbd clock */ -static struct clk usbd_clk = { - .pclk = &pll3_48m_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = USBD_CLK_ENB, - .recalc = &follow_parent, -}; - -/* clock derived from ahb clk */ -/* apb masks structure */ -static struct bus_clk_masks apb_masks = { - .mask = HCLK_PCLK_RATIO_MASK, - .shift = HCLK_PCLK_RATIO_SHIFT, -}; - -/* apb configuration structure */ -static struct bus_clk_config apb_config = { - .reg = CORE_CLK_CFG, - .masks = &apb_masks, -}; - -/* apb clock */ -static struct clk apb_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &ahb_clk, - .calc_rate = &bus_calc_rate, - .recalc = &bus_clk_recalc, - .set_rate = &bus_clk_set_rate, - .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2}, - .private_data = &apb_config, -}; - -/* i2c clock */ -static struct clk i2c_clk = { - .pclk = &ahb_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = I2C_CLK_ENB, - .recalc = &follow_parent, -}; - -/* dma clock */ -static struct clk dma_clk = { - .pclk = &ahb_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = DMA_CLK_ENB, - .recalc = &follow_parent, -}; - -/* jpeg clock */ -static struct clk jpeg_clk = { - .pclk = &ahb_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = JPEG_CLK_ENB, - .recalc = &follow_parent, -}; - -/* gmac clock */ -static struct clk gmac_clk = { - .pclk = &ahb_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = GMAC_CLK_ENB, - .recalc = &follow_parent, -}; - -/* smi clock */ -static struct clk smi_clk = { - .pclk = &ahb_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = SMI_CLK_ENB, - .recalc = &follow_parent, -}; - -/* fsmc clock */ -static struct clk fsmc_clk = { - .pclk = &ahb_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = FSMC_CLK_ENB, - .recalc = &follow_parent, -}; - -/* clock derived from apb clk */ -/* adc clock */ -static struct clk adc_clk = { - .pclk = &apb_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = ADC_CLK_ENB, - .recalc = &follow_parent, -}; - -/* ssp0 clock */ -static struct clk ssp0_clk = { - .pclk = &apb_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = SSP0_CLK_ENB, - .recalc = &follow_parent, -}; - -/* ssp1 clock */ -static struct clk ssp1_clk = { - .pclk = &apb_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = SSP1_CLK_ENB, - .recalc = &follow_parent, -}; - -/* ssp2 clock */ -static struct clk ssp2_clk = { - .pclk = &apb_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = SSP2_CLK_ENB, - .recalc = &follow_parent, -}; - -/* gpio0 ARM subsystem clock */ -static struct clk gpio0_clk = { - .flags = ALWAYS_ENABLED, - .pclk = &apb_clk, - .recalc = &follow_parent, -}; - -/* gpio1 clock */ -static struct clk gpio1_clk = { - .pclk = &apb_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = GPIO1_CLK_ENB, - .recalc = &follow_parent, -}; - -/* gpio2 clock */ -static struct clk gpio2_clk = { - .pclk = &apb_clk, - .en_reg = PERIP1_CLK_ENB, - .en_reg_bit = GPIO2_CLK_ENB, - .recalc = &follow_parent, -}; - -static struct clk dummy_apb_pclk; - -/* array of all spear 6xx clock lookups */ -static struct clk_lookup spear_clk_lookups[] = { - { .con_id = "apb_pclk", .clk = &dummy_apb_pclk}, - /* root clks */ - { .con_id = "osc_32k_clk", .clk = &osc_32k_clk}, - { .con_id = "osc_30m_clk", .clk = &osc_30m_clk}, - /* clock derived from 32 KHz os clk */ - { .dev_id = "rtc-spear", .clk = &rtc_clk}, - /* clock derived from 30 MHz os clk */ - { .con_id = "pll1_clk", .clk = &pll1_clk}, - { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk}, - { .dev_id = "wdt", .clk = &wdt_clk}, - /* clock derived from pll1 clk */ - { .con_id = "cpu_clk", .clk = &cpu_clk}, - { .con_id = "ahb_clk", .clk = &ahb_clk}, - { .con_id = "uart_synth_clk", .clk = &uart_synth_clk}, - { .con_id = "firda_synth_clk", .clk = &firda_synth_clk}, - { .con_id = "clcd_synth_clk", .clk = &clcd_synth_clk}, - { .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk}, - { .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk}, - { .con_id = "gpt3_synth_clk", .clk = &gpt3_synth_clk}, - { .dev_id = "d0000000.serial", .clk = &uart0_clk}, - { .dev_id = "d0080000.serial", .clk = &uart1_clk}, - { .dev_id = "firda", .clk = &firda_clk}, - { .dev_id = "clcd", .clk = &clcd_clk}, - { .dev_id = "gpt0", .clk = &gpt0_clk}, - { .dev_id = "gpt1", .clk = &gpt1_clk}, - { .dev_id = "gpt2", .clk = &gpt2_clk}, - { .dev_id = "gpt3", .clk = &gpt3_clk}, - /* clock derived from pll3 clk */ - { .dev_id = "designware_udc", .clk = &usbd_clk}, - { .con_id = "usbh.0_clk", .clk = &usbh0_clk}, - { .con_id = "usbh.1_clk", .clk = &usbh1_clk}, - /* clock derived from ahb clk */ - { .con_id = "apb_clk", .clk = &apb_clk}, - { .dev_id = "d0200000.i2c", .clk = &i2c_clk}, - { .dev_id = "dma", .clk = &dma_clk}, - { .dev_id = "jpeg", .clk = &jpeg_clk}, - { .dev_id = "gmac", .clk = &gmac_clk}, - { .dev_id = "smi", .clk = &smi_clk}, - { .dev_id = "fsmc-nand", .clk = &fsmc_clk}, - /* clock derived from apb clk */ - { .dev_id = "adc", .clk = &adc_clk}, - { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk}, - { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk}, - { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk}, - { .dev_id = "f0100000.gpio", .clk = &gpio0_clk}, - { .dev_id = "fc980000.gpio", .clk = &gpio1_clk}, - { .dev_id = "d8100000.gpio", .clk = &gpio2_clk}, -}; - -void __init spear6xx_clk_init(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) - clk_register(&spear_clk_lookups[i]); - - clk_init(); -} diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h index 116b99301cf5..65514b159370 100644 --- a/arch/arm/mach-spear6xx/include/mach/generic.h +++ b/arch/arm/mach-spear6xx/include/mach/generic.h @@ -15,34 +15,9 @@ #define __MACH_GENERIC_H #include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/amba/bus.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -/* - * Each GPT has 2 timer channels - * Following GPT channels will be used as clock source and clockevent - */ -#define SPEAR_GPT0_BASE SPEAR6XX_CPU_TMR_BASE -#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1 -#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2 - -/* Add spear6xx family device structure declarations here */ -extern struct amba_device gpio_device[]; -extern struct amba_device uart_device[]; -extern struct sys_timer spear6xx_timer; - -/* Add spear6xx family function declarations here */ -void __init spear_setup_timer(void); -void __init spear6xx_map_io(void); -void __init spear6xx_init_irq(void); -void __init spear6xx_init(void); -void __init spear600_init(void); -void __init spear6xx_clk_init(void); +void __init spear_setup_of_timer(void); void spear_restart(char, const char *); - -/* Add spear600 machine device structure declarations here */ +void __init spear6xx_clk_init(void); #endif /* __MACH_GENERIC_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/hardware.h b/arch/arm/mach-spear6xx/include/mach/hardware.h index 0b3f96ae2848..40a8c178f10d 100644 --- a/arch/arm/mach-spear6xx/include/mach/hardware.h +++ b/arch/arm/mach-spear6xx/include/mach/hardware.h @@ -1,23 +1 @@ -/* - * arch/arm/mach-spear6xx/include/mach/hardware.h - * - * Hardware definitions for SPEAr6xx machine family - * - * Copyright (C) 2009 ST Microelectronics - * Rajeev Kumar<rajeev-dlh.kumar@st.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_HARDWARE_H -#define __MACH_HARDWARE_H - -#include <plat/hardware.h> -#include <mach/spear.h> - -/* Vitual to physical translation of statically mapped space */ -#define IO_ADDRESS(x) (x | 0xF0000000) - -#endif /* __MACH_HARDWARE_H */ +/* empty */ diff --git a/arch/arm/mach-spear6xx/include/mach/irqs.h b/arch/arm/mach-spear6xx/include/mach/irqs.h index 8f214b03d75d..37a5c411a866 100644 --- a/arch/arm/mach-spear6xx/include/mach/irqs.h +++ b/arch/arm/mach-spear6xx/include/mach/irqs.h @@ -16,82 +16,10 @@ /* IRQ definitions */ /* VIC 1 */ -#define IRQ_INTRCOMM_SW_IRQ 0 -#define IRQ_INTRCOMM_CPU_1 1 -#define IRQ_INTRCOMM_CPU_2 2 -#define IRQ_INTRCOMM_RAS2A11_1 3 -#define IRQ_INTRCOMM_RAS2A11_2 4 -#define IRQ_INTRCOMM_RAS2A12_1 5 -#define IRQ_INTRCOMM_RAS2A12_2 6 -#define IRQ_GEN_RAS_0 7 -#define IRQ_GEN_RAS_1 8 -#define IRQ_GEN_RAS_2 9 -#define IRQ_GEN_RAS_3 10 -#define IRQ_GEN_RAS_4 11 -#define IRQ_GEN_RAS_5 12 -#define IRQ_GEN_RAS_6 13 -#define IRQ_GEN_RAS_7 14 -#define IRQ_GEN_RAS_8 15 -#define IRQ_CPU_GPT1_1 16 -#define IRQ_CPU_GPT1_2 17 -#define IRQ_LOCAL_GPIO 18 -#define IRQ_PLL_UNLOCK 19 -#define IRQ_JPEG 20 -#define IRQ_FSMC 21 -#define IRQ_IRDA 22 -#define IRQ_RESERVED 23 -#define IRQ_UART_0 24 -#define IRQ_UART_1 25 -#define IRQ_SSP_1 26 -#define IRQ_SSP_2 27 -#define IRQ_I2C 28 -#define IRQ_GEN_RAS_9 29 -#define IRQ_GEN_RAS_10 30 -#define IRQ_GEN_RAS_11 31 - -/* VIC 2 */ -#define IRQ_APPL_GPT1_1 32 -#define IRQ_APPL_GPT1_2 33 -#define IRQ_APPL_GPT2_1 34 -#define IRQ_APPL_GPT2_2 35 -#define IRQ_APPL_GPIO 36 -#define IRQ_APPL_SSP 37 -#define IRQ_APPL_ADC 38 -#define IRQ_APPL_RESERVED 39 -#define IRQ_AHB_EXP_MASTER 40 -#define IRQ_DDR_CONTROLLER 41 -#define IRQ_BASIC_DMA 42 -#define IRQ_BASIC_RESERVED1 43 -#define IRQ_BASIC_SMI 44 -#define IRQ_BASIC_CLCD 45 -#define IRQ_EXP_AHB_1 46 -#define IRQ_EXP_AHB_2 47 -#define IRQ_BASIC_GPT1_1 48 -#define IRQ_BASIC_GPT1_2 49 -#define IRQ_BASIC_RTC 50 -#define IRQ_BASIC_GPIO 51 -#define IRQ_BASIC_WDT 52 -#define IRQ_BASIC_RESERVED 53 -#define IRQ_AHB_EXP_SLAVE 54 -#define IRQ_GMAC_1 55 -#define IRQ_GMAC_2 56 -#define IRQ_USB_DEV 57 -#define IRQ_USB_H_OHCI_0 58 -#define IRQ_USB_H_EHCI_0 59 -#define IRQ_USB_H_OHCI_1 60 -#define IRQ_USB_H_EHCI_1 61 -#define IRQ_EXP_AHB_3 62 -#define IRQ_EXP_AHB_4 63 - #define IRQ_VIC_END 64 /* GPIO pins virtual irqs */ -#define SPEAR_GPIO_INT_BASE IRQ_VIC_END -#define SPEAR_GPIO0_INT_BASE SPEAR_GPIO_INT_BASE -#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO0_INT_BASE + 8) -#define SPEAR_GPIO2_INT_BASE (SPEAR_GPIO1_INT_BASE + 8) -#define SPEAR_GPIO_INT_END (SPEAR_GPIO2_INT_BASE + 8) -#define VIRTUAL_IRQS (SPEAR_GPIO_INT_END - IRQ_VIC_END) -#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) +#define VIRTUAL_IRQS 24 +#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) #endif /* __MACH_IRQS_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h index 68c20a007b0d..179e45774b3a 100644 --- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h +++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h @@ -14,161 +14,9 @@ #ifndef __MACH_MISC_REGS_H #define __MACH_MISC_REGS_H -#include <mach/hardware.h> +#include <mach/spear.h> #define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE) - -#define SOC_CFG_CTR (MISC_BASE + 0x000) -#define DIAG_CFG_CTR (MISC_BASE + 0x004) -#define PLL1_CTR (MISC_BASE + 0x008) -#define PLL1_FRQ (MISC_BASE + 0x00C) -#define PLL1_MOD (MISC_BASE + 0x010) -#define PLL2_CTR (MISC_BASE + 0x014) -/* PLL_CTR register masks */ -#define PLL_ENABLE 2 -#define PLL_MODE_SHIFT 4 -#define PLL_MODE_MASK 0x3 -#define PLL_MODE_NORMAL 0 -#define PLL_MODE_FRACTION 1 -#define PLL_MODE_DITH_DSB 2 -#define PLL_MODE_DITH_SSB 3 - -#define PLL2_FRQ (MISC_BASE + 0x018) -/* PLL FRQ register masks */ -#define PLL_DIV_N_SHIFT 0 -#define PLL_DIV_N_MASK 0xFF -#define PLL_DIV_P_SHIFT 8 -#define PLL_DIV_P_MASK 0x7 -#define PLL_NORM_FDBK_M_SHIFT 24 -#define PLL_NORM_FDBK_M_MASK 0xFF -#define PLL_DITH_FDBK_M_SHIFT 16 -#define PLL_DITH_FDBK_M_MASK 0xFFFF - -#define PLL2_MOD (MISC_BASE + 0x01C) -#define PLL_CLK_CFG (MISC_BASE + 0x020) -#define CORE_CLK_CFG (MISC_BASE + 0x024) -/* CORE CLK CFG register masks */ -#define PLL_HCLK_RATIO_SHIFT 10 -#define PLL_HCLK_RATIO_MASK 0x3 -#define HCLK_PCLK_RATIO_SHIFT 8 -#define HCLK_PCLK_RATIO_MASK 0x3 - -#define PERIP_CLK_CFG (MISC_BASE + 0x028) -/* PERIP_CLK_CFG register masks */ -#define CLCD_CLK_SHIFT 2 -#define CLCD_CLK_MASK 0x3 -#define UART_CLK_SHIFT 4 -#define UART_CLK_MASK 0x1 -#define FIRDA_CLK_SHIFT 5 -#define FIRDA_CLK_MASK 0x3 -#define GPT0_CLK_SHIFT 8 -#define GPT1_CLK_SHIFT 10 -#define GPT2_CLK_SHIFT 11 -#define GPT3_CLK_SHIFT 12 -#define GPT_CLK_MASK 0x1 -#define AUX_CLK_PLL3_VAL 0 -#define AUX_CLK_PLL1_VAL 1 - -#define PERIP1_CLK_ENB (MISC_BASE + 0x02C) -/* PERIP1_CLK_ENB register masks */ -#define UART0_CLK_ENB 3 -#define UART1_CLK_ENB 4 -#define SSP0_CLK_ENB 5 -#define SSP1_CLK_ENB 6 -#define I2C_CLK_ENB 7 -#define JPEG_CLK_ENB 8 -#define FSMC_CLK_ENB 9 -#define FIRDA_CLK_ENB 10 -#define GPT2_CLK_ENB 11 -#define GPT3_CLK_ENB 12 -#define GPIO2_CLK_ENB 13 -#define SSP2_CLK_ENB 14 -#define ADC_CLK_ENB 15 -#define GPT1_CLK_ENB 11 -#define RTC_CLK_ENB 17 -#define GPIO1_CLK_ENB 18 -#define DMA_CLK_ENB 19 -#define SMI_CLK_ENB 21 -#define CLCD_CLK_ENB 22 -#define GMAC_CLK_ENB 23 -#define USBD_CLK_ENB 24 -#define USBH0_CLK_ENB 25 -#define USBH1_CLK_ENB 26 - -#define SOC_CORE_ID (MISC_BASE + 0x030) -#define RAS_CLK_ENB (MISC_BASE + 0x034) -#define PERIP1_SOF_RST (MISC_BASE + 0x038) -/* PERIP1_SOF_RST register masks */ -#define JPEG_SOF_RST 8 - -#define SOC_USER_ID (MISC_BASE + 0x03C) -#define RAS_SOF_RST (MISC_BASE + 0x040) -#define PRSC1_CLK_CFG (MISC_BASE + 0x044) -#define PRSC2_CLK_CFG (MISC_BASE + 0x048) -#define PRSC3_CLK_CFG (MISC_BASE + 0x04C) -/* gpt synthesizer register masks */ -#define GPT_MSCALE_SHIFT 0 -#define GPT_MSCALE_MASK 0xFFF -#define GPT_NSCALE_SHIFT 12 -#define GPT_NSCALE_MASK 0xF - -#define AMEM_CLK_CFG (MISC_BASE + 0x050) -#define EXPI_CLK_CFG (MISC_BASE + 0x054) -#define CLCD_CLK_SYNT (MISC_BASE + 0x05C) -#define FIRDA_CLK_SYNT (MISC_BASE + 0x060) -#define UART_CLK_SYNT (MISC_BASE + 0x064) -#define GMAC_CLK_SYNT (MISC_BASE + 0x068) -#define RAS1_CLK_SYNT (MISC_BASE + 0x06C) -#define RAS2_CLK_SYNT (MISC_BASE + 0x070) -#define RAS3_CLK_SYNT (MISC_BASE + 0x074) -#define RAS4_CLK_SYNT (MISC_BASE + 0x078) -/* aux clk synthesiser register masks for irda to ras4 */ -#define AUX_SYNT_ENB 31 -#define AUX_EQ_SEL_SHIFT 30 -#define AUX_EQ_SEL_MASK 1 -#define AUX_EQ1_SEL 0 -#define AUX_EQ2_SEL 1 -#define AUX_XSCALE_SHIFT 16 -#define AUX_XSCALE_MASK 0xFFF -#define AUX_YSCALE_SHIFT 0 -#define AUX_YSCALE_MASK 0xFFF - -#define ICM1_ARB_CFG (MISC_BASE + 0x07C) -#define ICM2_ARB_CFG (MISC_BASE + 0x080) -#define ICM3_ARB_CFG (MISC_BASE + 0x084) -#define ICM4_ARB_CFG (MISC_BASE + 0x088) -#define ICM5_ARB_CFG (MISC_BASE + 0x08C) -#define ICM6_ARB_CFG (MISC_BASE + 0x090) -#define ICM7_ARB_CFG (MISC_BASE + 0x094) -#define ICM8_ARB_CFG (MISC_BASE + 0x098) -#define ICM9_ARB_CFG (MISC_BASE + 0x09C) #define DMA_CHN_CFG (MISC_BASE + 0x0A0) -#define USB2_PHY_CFG (MISC_BASE + 0x0A4) -#define GMAC_CFG_CTR (MISC_BASE + 0x0A8) -#define EXPI_CFG_CTR (MISC_BASE + 0x0AC) -#define PRC1_LOCK_CTR (MISC_BASE + 0x0C0) -#define PRC2_LOCK_CTR (MISC_BASE + 0x0C4) -#define PRC3_LOCK_CTR (MISC_BASE + 0x0C8) -#define PRC4_LOCK_CTR (MISC_BASE + 0x0CC) -#define PRC1_IRQ_CTR (MISC_BASE + 0x0D0) -#define PRC2_IRQ_CTR (MISC_BASE + 0x0D4) -#define PRC3_IRQ_CTR (MISC_BASE + 0x0D8) -#define PRC4_IRQ_CTR (MISC_BASE + 0x0DC) -#define PWRDOWN_CFG_CTR (MISC_BASE + 0x0E0) -#define COMPSSTL_1V8_CFG (MISC_BASE + 0x0E4) -#define COMPSSTL_2V5_CFG (MISC_BASE + 0x0E8) -#define COMPCOR_3V3_CFG (MISC_BASE + 0x0EC) -#define SSTLPAD_CFG_CTR (MISC_BASE + 0x0F0) -#define BIST1_CFG_CTR (MISC_BASE + 0x0F4) -#define BIST2_CFG_CTR (MISC_BASE + 0x0F8) -#define BIST3_CFG_CTR (MISC_BASE + 0x0FC) -#define BIST4_CFG_CTR (MISC_BASE + 0x100) -#define BIST5_CFG_CTR (MISC_BASE + 0x104) -#define BIST1_STS_RES (MISC_BASE + 0x108) -#define BIST2_STS_RES (MISC_BASE + 0x10C) -#define BIST3_STS_RES (MISC_BASE + 0x110) -#define BIST4_STS_RES (MISC_BASE + 0x114) -#define BIST5_STS_RES (MISC_BASE + 0x118) -#define SYSERR_CFG_CTR (MISC_BASE + 0x11C) #endif /* __MACH_MISC_REGS_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h index 7fd621532def..cb8ed2f4dc85 100644 --- a/arch/arm/mach-spear6xx/include/mach/spear.h +++ b/arch/arm/mach-spear6xx/include/mach/spear.h @@ -15,69 +15,25 @@ #define __MACH_SPEAR6XX_H #include <asm/memory.h> -#include <mach/spear600.h> -#define SPEAR6XX_ML_SDRAM_BASE UL(0x00000000) /* ICM1 - Low speed connection */ #define SPEAR6XX_ICM1_BASE UL(0xD0000000) - +#define VA_SPEAR6XX_ICM1_BASE UL(0xFD000000) #define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000) -#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE) - -#define SPEAR6XX_ICM1_UART1_BASE UL(0xD0080000) -#define SPEAR6XX_ICM1_SSP0_BASE UL(0xD0100000) -#define SPEAR6XX_ICM1_SSP1_BASE UL(0xD0180000) -#define SPEAR6XX_ICM1_I2C_BASE UL(0xD0200000) -#define SPEAR6XX_ICM1_JPEG_BASE UL(0xD0800000) -#define SPEAR6XX_ICM1_IRDA_BASE UL(0xD1000000) -#define SPEAR6XX_ICM1_FSMC_BASE UL(0xD1800000) -#define SPEAR6XX_ICM1_NAND_BASE UL(0xD2000000) -#define SPEAR6XX_ICM1_SRAM_BASE UL(0xD2800000) - -/* ICM2 - Application Subsystem */ -#define SPEAR6XX_ICM2_BASE UL(0xD8000000) -#define SPEAR6XX_ICM2_TMR0_BASE UL(0xD8000000) -#define SPEAR6XX_ICM2_TMR1_BASE UL(0xD8080000) -#define SPEAR6XX_ICM2_GPIO_BASE UL(0xD8100000) -#define SPEAR6XX_ICM2_SSP2_BASE UL(0xD8180000) -#define SPEAR6XX_ICM2_ADC_BASE UL(0xD8200000) +#define VA_SPEAR6XX_ICM1_UART0_BASE (VA_SPEAR6XX_ICM1_2_BASE | SPEAR6XX_ICM1_UART0_BASE) /* ML-1, 2 - Multi Layer CPU Subsystem */ #define SPEAR6XX_ML_CPU_BASE UL(0xF0000000) -#define SPEAR6XX_CPU_TMR_BASE UL(0xF0000000) -#define SPEAR6XX_CPU_GPIO_BASE UL(0xF0100000) -#define SPEAR6XX_CPU_VIC_SEC_BASE UL(0xF1000000) -#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE) -#define SPEAR6XX_CPU_VIC_PRI_BASE UL(0xF1100000) -#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE) +#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000) /* ICM3 - Basic Subsystem */ -#define SPEAR6XX_ICM3_BASE UL(0xF8000000) -#define SPEAR6XX_ICM3_SMEM_BASE UL(0xF8000000) #define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) -#define SPEAR6XX_ICM3_CLCD_BASE UL(0xFC200000) +#define VA_SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) #define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000) -#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000) -#define SPEAR6XX_ICM3_TMR_BASE UL(0xFC800000) -#define SPEAR6XX_ICM3_WDT_BASE UL(0xFC880000) -#define SPEAR6XX_ICM3_RTC_BASE UL(0xFC900000) -#define SPEAR6XX_ICM3_GPIO_BASE UL(0xFC980000) #define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) -#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE) +#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_SYS_CTRL_BASE) #define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000) -#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE) - -/* ICM4 - High Speed Connection */ -#define SPEAR6XX_ICM4_BASE UL(0xE0000000) -#define SPEAR6XX_ICM4_GMAC_BASE UL(0xE0800000) -#define SPEAR6XX_ICM4_USBD_FIFO_BASE UL(0xE1000000) -#define SPEAR6XX_ICM4_USBD_CSR_BASE UL(0xE1100000) -#define SPEAR6XX_ICM4_USBD_PLDT_BASE UL(0xE1200000) -#define SPEAR6XX_ICM4_USB_EHCI0_BASE UL(0xE1800000) -#define SPEAR6XX_ICM4_USB_OHCI0_BASE UL(0xE1900000) -#define SPEAR6XX_ICM4_USB_EHCI1_BASE UL(0xE2000000) -#define SPEAR6XX_ICM4_USB_OHCI1_BASE UL(0xE2100000) -#define SPEAR6XX_ICM4_USB_ARB_BASE UL(0xE2800000) +#define VA_SPEAR6XX_ICM3_MISC_REG_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_MISC_REG_BASE) /* Debug uart for linux, will be used for debug and uncompress messages */ #define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE diff --git a/arch/arm/mach-spear6xx/include/mach/spear600.h b/arch/arm/mach-spear6xx/include/mach/spear600.h deleted file mode 100644 index c068cc50b0fb..000000000000 --- a/arch/arm/mach-spear6xx/include/mach/spear600.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * arch/arm/mach-spear66xx/include/mach/spear600.h - * - * SPEAr600 Machine specific definition - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifdef CONFIG_MACH_SPEAR600 - -#ifndef __MACH_SPEAR600_H -#define __MACH_SPEAR600_H - -#endif /* __MACH_SPEAR600_H */ - -#endif /* CONFIG_MACH_SPEAR600 */ diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c index 2ed8b14c82c8..2e2e3596583e 100644 --- a/arch/arm/mach-spear6xx/spear6xx.c +++ b/arch/arm/mach-spear6xx/spear6xx.c @@ -13,41 +13,404 @@ * warranty of any kind, whether express or implied. */ +#include <linux/amba/pl08x.h> +#include <linux/clk.h> +#include <linux/err.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/of_platform.h> +#include <asm/hardware/pl080.h> #include <asm/hardware/vic.h> #include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <asm/mach/map.h> +#include <plat/pl080.h> #include <mach/generic.h> -#include <mach/hardware.h> +#include <mach/spear.h> -/* Following will create static virtual/physical mappings */ -static struct map_desc spear6xx_io_desc[] __initdata = { +/* dmac device registration */ +static struct pl08x_channel_data spear600_dma_info[] = { { - .virtual = VA_SPEAR6XX_ICM1_UART0_BASE, - .pfn = __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE), - .length = SZ_4K, - .type = MT_DEVICE + .bus_id = "ssp1_rx", + .min_signal = 0, + .max_signal = 0, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, }, { - .virtual = VA_SPEAR6XX_CPU_VIC_PRI_BASE, - .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE), - .length = SZ_4K, - .type = MT_DEVICE + .bus_id = "ssp1_tx", + .min_signal = 1, + .max_signal = 1, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, }, { - .virtual = VA_SPEAR6XX_CPU_VIC_SEC_BASE, - .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE), - .length = SZ_4K, - .type = MT_DEVICE + .bus_id = "uart0_rx", + .min_signal = 2, + .max_signal = 2, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart0_tx", + .min_signal = 3, + .max_signal = 3, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart1_rx", + .min_signal = 4, + .max_signal = 4, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "uart1_tx", + .min_signal = 5, + .max_signal = 5, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ssp2_rx", + .min_signal = 6, + .max_signal = 6, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ssp2_tx", + .min_signal = 7, + .max_signal = 7, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ssp0_rx", + .min_signal = 8, + .max_signal = 8, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ssp0_tx", + .min_signal = 9, + .max_signal = 9, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "i2c_rx", + .min_signal = 10, + .max_signal = 10, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "i2c_tx", + .min_signal = 11, + .max_signal = 11, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "irda", + .min_signal = 12, + .max_signal = 12, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "adc", + .min_signal = 13, + .max_signal = 13, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "to_jpeg", + .min_signal = 14, + .max_signal = 14, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "from_jpeg", + .min_signal = 15, + .max_signal = 15, + .muxval = 0, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras0_rx", + .min_signal = 0, + .max_signal = 0, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras0_tx", + .min_signal = 1, + .max_signal = 1, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras1_rx", + .min_signal = 2, + .max_signal = 2, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras1_tx", + .min_signal = 3, + .max_signal = 3, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras2_rx", + .min_signal = 4, + .max_signal = 4, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras2_tx", + .min_signal = 5, + .max_signal = 5, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras3_rx", + .min_signal = 6, + .max_signal = 6, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras3_tx", + .min_signal = 7, + .max_signal = 7, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras4_rx", + .min_signal = 8, + .max_signal = 8, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras4_tx", + .min_signal = 9, + .max_signal = 9, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras5_rx", + .min_signal = 10, + .max_signal = 10, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras5_tx", + .min_signal = 11, + .max_signal = 11, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras6_rx", + .min_signal = 12, + .max_signal = 12, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras6_tx", + .min_signal = 13, + .max_signal = 13, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras7_rx", + .min_signal = 14, + .max_signal = 14, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, + }, { + .bus_id = "ras7_tx", + .min_signal = 15, + .max_signal = 15, + .muxval = 1, + .cctl = 0, + .periph_buses = PL08X_AHB1, }, { - .virtual = VA_SPEAR6XX_ICM3_SYS_CTRL_BASE, - .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE), - .length = SZ_4K, + .bus_id = "ext0_rx", + .min_signal = 0, + .max_signal = 0, + .muxval = 2, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext0_tx", + .min_signal = 1, + .max_signal = 1, + .muxval = 2, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext1_rx", + .min_signal = 2, + .max_signal = 2, + .muxval = 2, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext1_tx", + .min_signal = 3, + .max_signal = 3, + .muxval = 2, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext2_rx", + .min_signal = 4, + .max_signal = 4, + .muxval = 2, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext2_tx", + .min_signal = 5, + .max_signal = 5, + .muxval = 2, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext3_rx", + .min_signal = 6, + .max_signal = 6, + .muxval = 2, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext3_tx", + .min_signal = 7, + .max_signal = 7, + .muxval = 2, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext4_rx", + .min_signal = 8, + .max_signal = 8, + .muxval = 2, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext4_tx", + .min_signal = 9, + .max_signal = 9, + .muxval = 2, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext5_rx", + .min_signal = 10, + .max_signal = 10, + .muxval = 2, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext5_tx", + .min_signal = 11, + .max_signal = 11, + .muxval = 2, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext6_rx", + .min_signal = 12, + .max_signal = 12, + .muxval = 2, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext6_tx", + .min_signal = 13, + .max_signal = 13, + .muxval = 2, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext7_rx", + .min_signal = 14, + .max_signal = 14, + .muxval = 2, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, { + .bus_id = "ext7_tx", + .min_signal = 15, + .max_signal = 15, + .muxval = 2, + .cctl = 0, + .periph_buses = PL08X_AHB2, + }, +}; + +struct pl08x_platform_data pl080_plat_data = { + .memcpy_channel = { + .bus_id = "memcpy", + .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \ + PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \ + PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \ + PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \ + PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \ + PL080_CONTROL_PROT_SYS), + }, + .lli_buses = PL08X_AHB1, + .mem_buses = PL08X_AHB1, + .get_signal = pl080_get_signal, + .put_signal = pl080_put_signal, + .slave_channels = spear600_dma_info, + .num_slave_channels = ARRAY_SIZE(spear600_dma_info), +}; + +/* + * Following will create 16MB static virtual/physical mappings + * PHYSICAL VIRTUAL + * 0xF0000000 0xF0000000 + * 0xF1000000 0xF1000000 + * 0xD0000000 0xFD000000 + * 0xFC000000 0xFC000000 + */ +struct map_desc spear6xx_io_desc[] __initdata = { + { + .virtual = VA_SPEAR6XX_ML_CPU_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE), + .length = 2 * SZ_16M, + .type = MT_DEVICE + }, { + .virtual = VA_SPEAR6XX_ICM1_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_ICM1_BASE), + .length = SZ_16M, .type = MT_DEVICE }, { - .virtual = VA_SPEAR6XX_ICM3_MISC_REG_BASE, - .pfn = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE), - .length = SZ_4K, + .virtual = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE), + .length = SZ_16M, .type = MT_DEVICE }, }; @@ -56,9 +419,6 @@ static struct map_desc spear6xx_io_desc[] __initdata = { void __init spear6xx_map_io(void) { iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc)); - - /* This will initialize clock framework */ - spear6xx_clk_init(); } static void __init spear6xx_timer_init(void) @@ -66,6 +426,8 @@ static void __init spear6xx_timer_init(void) char pclk_name[] = "pll3_48m_clk"; struct clk *gpt_clk, *pclk; + spear6xx_clk_init(); + /* get the system timer clock */ gpt_clk = clk_get_sys("gpt0", NULL); if (IS_ERR(gpt_clk)) { @@ -85,16 +447,24 @@ static void __init spear6xx_timer_init(void) clk_put(gpt_clk); clk_put(pclk); - spear_setup_timer(); + spear_setup_of_timer(); } struct sys_timer spear6xx_timer = { .init = spear6xx_timer_init, }; +/* Add auxdata to pass platform data */ +struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL, + &pl080_plat_data), + {} +}; + static void __init spear600_dt_init(void) { - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + of_platform_populate(NULL, of_default_bus_match_table, + spear6xx_auxdata_lookup, NULL); } static const char *spear600_dt_board_compat[] = { diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig index 1bb3dbce8810..4404f82d5979 100644 --- a/arch/arm/plat-spear/Kconfig +++ b/arch/arm/plat-spear/Kconfig @@ -8,10 +8,23 @@ choice prompt "ST SPEAr Family" default ARCH_SPEAR3XX +config ARCH_SPEAR13XX + bool "ST SPEAr13xx with Device Tree" + select ARM_GIC + select CPU_V7 + select USE_OF + select HAVE_SMP + select MIGHT_HAVE_CACHE_L2X0 + select PINCTRL + help + Supports for ARM's SPEAR13XX family + config ARCH_SPEAR3XX - bool "SPEAr3XX" + bool "ST SPEAr3xx with Device Tree" select ARM_VIC select CPU_ARM926T + select USE_OF + select PINCTRL help Supports for ARM's SPEAR3XX family @@ -25,6 +38,7 @@ config ARCH_SPEAR6XX endchoice # Adding SPEAr machine specific configuration files +source "arch/arm/mach-spear13xx/Kconfig" source "arch/arm/mach-spear3xx/Kconfig" source "arch/arm/mach-spear6xx/Kconfig" diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile index e0f2e5b9530c..2607bd05c525 100644 --- a/arch/arm/plat-spear/Makefile +++ b/arch/arm/plat-spear/Makefile @@ -3,6 +3,7 @@ # # Common support -obj-y := clock.o restart.o time.o +obj-y := restart.o time.o -obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o +obj-$(CONFIG_ARCH_SPEAR3XX) += pl080.o shirq.o +obj-$(CONFIG_ARCH_SPEAR6XX) += pl080.o diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c deleted file mode 100644 index 67dd00381ea6..000000000000 --- a/arch/arm/plat-spear/clock.c +++ /dev/null @@ -1,1005 +0,0 @@ -/* - * arch/arm/plat-spear/clock.c - * - * Clock framework for SPEAr platform - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/bug.h> -#include <linux/clk.h> -#include <linux/debugfs.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/list.h> -#include <linux/module.h> -#include <linux/spinlock.h> -#include <plat/clock.h> - -static DEFINE_SPINLOCK(clocks_lock); -static LIST_HEAD(root_clks); -#ifdef CONFIG_DEBUG_FS -static LIST_HEAD(clocks); -#endif - -static void propagate_rate(struct clk *, int on_init); -#ifdef CONFIG_DEBUG_FS -static int clk_debugfs_reparent(struct clk *); -#endif - -static int generic_clk_enable(struct clk *clk) -{ - unsigned int val; - - if (!clk->en_reg) - return -EFAULT; - - val = readl(clk->en_reg); - if (unlikely(clk->flags & RESET_TO_ENABLE)) - val &= ~(1 << clk->en_reg_bit); - else - val |= 1 << clk->en_reg_bit; - - writel(val, clk->en_reg); - - return 0; -} - -static void generic_clk_disable(struct clk *clk) -{ - unsigned int val; - - if (!clk->en_reg) - return; - - val = readl(clk->en_reg); - if (unlikely(clk->flags & RESET_TO_ENABLE)) - val |= 1 << clk->en_reg_bit; - else - val &= ~(1 << clk->en_reg_bit); - - writel(val, clk->en_reg); -} - -/* generic clk ops */ -static struct clkops generic_clkops = { - .enable = generic_clk_enable, - .disable = generic_clk_disable, -}; - -/* returns current programmed clocks clock info structure */ -static struct pclk_info *pclk_info_get(struct clk *clk) -{ - unsigned int val, i; - struct pclk_info *info = NULL; - - val = (readl(clk->pclk_sel->pclk_sel_reg) >> clk->pclk_sel_shift) - & clk->pclk_sel->pclk_sel_mask; - - for (i = 0; i < clk->pclk_sel->pclk_count; i++) { - if (clk->pclk_sel->pclk_info[i].pclk_val == val) - info = &clk->pclk_sel->pclk_info[i]; - } - - return info; -} - -/* - * Set Update pclk, and pclk_info of clk and add clock sibling node to current - * parents children list - */ -static void clk_reparent(struct clk *clk, struct pclk_info *pclk_info) -{ - unsigned long flags; - - spin_lock_irqsave(&clocks_lock, flags); - list_del(&clk->sibling); - list_add(&clk->sibling, &pclk_info->pclk->children); - - clk->pclk = pclk_info->pclk; - spin_unlock_irqrestore(&clocks_lock, flags); - -#ifdef CONFIG_DEBUG_FS - clk_debugfs_reparent(clk); -#endif -} - -static void do_clk_disable(struct clk *clk) -{ - if (!clk) - return; - - if (!clk->usage_count) { - WARN_ON(1); - return; - } - - clk->usage_count--; - - if (clk->usage_count == 0) { - /* - * Surely, there are no active childrens or direct users - * of this clock - */ - if (clk->pclk) - do_clk_disable(clk->pclk); - - if (clk->ops && clk->ops->disable) - clk->ops->disable(clk); - } -} - -static int do_clk_enable(struct clk *clk) -{ - int ret = 0; - - if (!clk) - return -EFAULT; - - if (clk->usage_count == 0) { - if (clk->pclk) { - ret = do_clk_enable(clk->pclk); - if (ret) - goto err; - } - if (clk->ops && clk->ops->enable) { - ret = clk->ops->enable(clk); - if (ret) { - if (clk->pclk) - do_clk_disable(clk->pclk); - goto err; - } - } - /* - * Since the clock is going to be used for the first - * time please reclac - */ - if (clk->recalc) { - ret = clk->recalc(clk); - if (ret) - goto err; - } - } - clk->usage_count++; -err: - return ret; -} - -/* - * clk_enable - inform the system when the clock source should be running. - * @clk: clock source - * - * If the clock can not be enabled/disabled, this should return success. - * - * Returns success (0) or negative errno. - */ -int clk_enable(struct clk *clk) -{ - unsigned long flags; - int ret = 0; - - spin_lock_irqsave(&clocks_lock, flags); - ret = do_clk_enable(clk); - spin_unlock_irqrestore(&clocks_lock, flags); - return ret; -} -EXPORT_SYMBOL(clk_enable); - -/* - * clk_disable - inform the system when the clock source is no longer required. - * @clk: clock source - * - * Inform the system that a clock source is no longer required by - * a driver and may be shut down. - * - * Implementation detail: if the clock source is shared between - * multiple drivers, clk_enable() calls must be balanced by the - * same number of clk_disable() calls for the clock source to be - * disabled. - */ -void clk_disable(struct clk *clk) -{ - unsigned long flags; - - spin_lock_irqsave(&clocks_lock, flags); - do_clk_disable(clk); - spin_unlock_irqrestore(&clocks_lock, flags); -} -EXPORT_SYMBOL(clk_disable); - -/** - * clk_get_rate - obtain the current clock rate (in Hz) for a clock source. - * This is only valid once the clock source has been enabled. - * @clk: clock source - */ -unsigned long clk_get_rate(struct clk *clk) -{ - unsigned long flags, rate; - - spin_lock_irqsave(&clocks_lock, flags); - rate = clk->rate; - spin_unlock_irqrestore(&clocks_lock, flags); - - return rate; -} -EXPORT_SYMBOL(clk_get_rate); - -/** - * clk_set_parent - set the parent clock source for this clock - * @clk: clock source - * @parent: parent clock source - * - * Returns success (0) or negative errno. - */ -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - int i, found = 0, val = 0; - unsigned long flags; - - if (!clk || !parent) - return -EFAULT; - if (clk->pclk == parent) - return 0; - if (!clk->pclk_sel) - return -EPERM; - - /* check if requested parent is in clk parent list */ - for (i = 0; i < clk->pclk_sel->pclk_count; i++) { - if (clk->pclk_sel->pclk_info[i].pclk == parent) { - found = 1; - break; - } - } - - if (!found) - return -EINVAL; - - spin_lock_irqsave(&clocks_lock, flags); - /* reflect parent change in hardware */ - val = readl(clk->pclk_sel->pclk_sel_reg); - val &= ~(clk->pclk_sel->pclk_sel_mask << clk->pclk_sel_shift); - val |= clk->pclk_sel->pclk_info[i].pclk_val << clk->pclk_sel_shift; - writel(val, clk->pclk_sel->pclk_sel_reg); - spin_unlock_irqrestore(&clocks_lock, flags); - - /* reflect parent change in software */ - clk_reparent(clk, &clk->pclk_sel->pclk_info[i]); - - propagate_rate(clk, 0); - return 0; -} -EXPORT_SYMBOL(clk_set_parent); - -/** - * clk_set_rate - set the clock rate for a clock source - * @clk: clock source - * @rate: desired clock rate in Hz - * - * Returns success (0) or negative errno. - */ -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - unsigned long flags; - int ret = -EINVAL; - - if (!clk || !rate) - return -EFAULT; - - if (clk->set_rate) { - spin_lock_irqsave(&clocks_lock, flags); - ret = clk->set_rate(clk, rate); - if (!ret) - /* if successful -> propagate */ - propagate_rate(clk, 0); - spin_unlock_irqrestore(&clocks_lock, flags); - } else if (clk->pclk) { - u32 mult = clk->div_factor ? clk->div_factor : 1; - ret = clk_set_rate(clk->pclk, mult * rate); - } - - return ret; -} -EXPORT_SYMBOL(clk_set_rate); - -/* registers clock in platform clock framework */ -void clk_register(struct clk_lookup *cl) -{ - struct clk *clk; - unsigned long flags; - - if (!cl || !cl->clk) - return; - clk = cl->clk; - - spin_lock_irqsave(&clocks_lock, flags); - - INIT_LIST_HEAD(&clk->children); - if (clk->flags & ALWAYS_ENABLED) - clk->ops = NULL; - else if (!clk->ops) - clk->ops = &generic_clkops; - - /* root clock don't have any parents */ - if (!clk->pclk && !clk->pclk_sel) { - list_add(&clk->sibling, &root_clks); - } else if (clk->pclk && !clk->pclk_sel) { - /* add clocks with only one parent to parent's children list */ - list_add(&clk->sibling, &clk->pclk->children); - } else { - /* clocks with more than one parent */ - struct pclk_info *pclk_info; - - pclk_info = pclk_info_get(clk); - if (!pclk_info) { - pr_err("CLKDEV: invalid pclk info of clk with" - " %s dev_id and %s con_id\n", - cl->dev_id, cl->con_id); - } else { - clk->pclk = pclk_info->pclk; - list_add(&clk->sibling, &pclk_info->pclk->children); - } - } - - spin_unlock_irqrestore(&clocks_lock, flags); - - /* debugfs specific */ -#ifdef CONFIG_DEBUG_FS - list_add(&clk->node, &clocks); - clk->cl = cl; -#endif - - /* add clock to arm clockdev framework */ - clkdev_add(cl); -} - -/** - * propagate_rate - recalculate and propagate all clocks to children - * @pclk: parent clock required to be propogated - * @on_init: flag for enabling clocks which are ENABLED_ON_INIT. - * - * Recalculates all children clocks - */ -void propagate_rate(struct clk *pclk, int on_init) -{ - struct clk *clk, *_temp; - int ret = 0; - - list_for_each_entry_safe(clk, _temp, &pclk->children, sibling) { - if (clk->recalc) { - ret = clk->recalc(clk); - /* - * recalc will return error if clk out is not programmed - * In this case configure default rate. - */ - if (ret && clk->set_rate) - clk->set_rate(clk, 0); - } - propagate_rate(clk, on_init); - - if (!on_init) - continue; - - /* Enable clks enabled on init, in software view */ - if (clk->flags & ENABLED_ON_INIT) - do_clk_enable(clk); - } -} - -/** - * round_rate_index - return closest programmable rate index in rate_config tbl - * @clk: ptr to clock structure - * @drate: desired rate - * @rate: final rate will be returned in this variable only. - * - * Finds index in rate_config for highest clk rate which is less than - * requested rate. If there is no clk rate lesser than requested rate then - * -EINVAL is returned. This routine assumes that rate_config is written - * in incrementing order of clk rates. - * If drate passed is zero then default rate is programmed. - */ -static int -round_rate_index(struct clk *clk, unsigned long drate, unsigned long *rate) -{ - unsigned long tmp = 0, prev_rate = 0; - int index; - - if (!clk->calc_rate) - return -EFAULT; - - if (!drate) - return -EINVAL; - - /* - * This loops ends on two conditions: - * - as soon as clk is found with rate greater than requested rate. - * - if all clks in rate_config are smaller than requested rate. - */ - for (index = 0; index < clk->rate_config.count; index++) { - prev_rate = tmp; - tmp = clk->calc_rate(clk, index); - if (drate < tmp) { - index--; - break; - } - } - /* return if can't find suitable clock */ - if (index < 0) { - index = -EINVAL; - *rate = 0; - } else if (index == clk->rate_config.count) { - /* program with highest clk rate possible */ - index = clk->rate_config.count - 1; - *rate = tmp; - } else - *rate = prev_rate; - - return index; -} - -/** - * clk_round_rate - adjust a rate to the exact rate a clock can provide - * @clk: clock source - * @rate: desired clock rate in Hz - * - * Returns rounded clock rate in Hz, or negative errno. - */ -long clk_round_rate(struct clk *clk, unsigned long drate) -{ - long rate = 0; - int index; - - /* - * propagate call to parent who supports calc_rate. Similar approach is - * used in clk_set_rate. - */ - if (!clk->calc_rate) { - u32 mult; - if (!clk->pclk) - return clk->rate; - - mult = clk->div_factor ? clk->div_factor : 1; - return clk_round_rate(clk->pclk, mult * drate) / mult; - } - - index = round_rate_index(clk, drate, &rate); - if (index >= 0) - return rate; - else - return index; -} -EXPORT_SYMBOL(clk_round_rate); - -/*All below functions are called with lock held */ - -/* - * Calculates pll clk rate for specific value of mode, m, n and p - * - * In normal mode - * rate = (2 * M[15:8] * Fin)/(N * 2^P) - * - * In Dithered mode - * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P) - */ -unsigned long pll_calc_rate(struct clk *clk, int index) -{ - unsigned long rate = clk->pclk->rate; - struct pll_rate_tbl *tbls = clk->rate_config.tbls; - unsigned int mode; - - mode = tbls[index].mode ? 256 : 1; - return (((2 * rate / 10000) * tbls[index].m) / - (mode * tbls[index].n * (1 << tbls[index].p))) * 10000; -} - -/* - * calculates current programmed rate of pll1 - * - * In normal mode - * rate = (2 * M[15:8] * Fin)/(N * 2^P) - * - * In Dithered mode - * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P) - */ -int pll_clk_recalc(struct clk *clk) -{ - struct pll_clk_config *config = clk->private_data; - unsigned int num = 2, den = 0, val, mode = 0; - - mode = (readl(config->mode_reg) >> config->masks->mode_shift) & - config->masks->mode_mask; - - val = readl(config->cfg_reg); - /* calculate denominator */ - den = (val >> config->masks->div_p_shift) & config->masks->div_p_mask; - den = 1 << den; - den *= (val >> config->masks->div_n_shift) & config->masks->div_n_mask; - - /* calculate numerator & denominator */ - if (!mode) { - /* Normal mode */ - num *= (val >> config->masks->norm_fdbk_m_shift) & - config->masks->norm_fdbk_m_mask; - } else { - /* Dithered mode */ - num *= (val >> config->masks->dith_fdbk_m_shift) & - config->masks->dith_fdbk_m_mask; - den *= 256; - } - - if (!den) - return -EINVAL; - - clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000; - return 0; -} - -/* - * Configures new clock rate of pll - */ -int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate) -{ - struct pll_rate_tbl *tbls = clk->rate_config.tbls; - struct pll_clk_config *config = clk->private_data; - unsigned long val, rate; - int i; - - i = round_rate_index(clk, desired_rate, &rate); - if (i < 0) - return i; - - val = readl(config->mode_reg) & - ~(config->masks->mode_mask << config->masks->mode_shift); - val |= (tbls[i].mode & config->masks->mode_mask) << - config->masks->mode_shift; - writel(val, config->mode_reg); - - val = readl(config->cfg_reg) & - ~(config->masks->div_p_mask << config->masks->div_p_shift); - val |= (tbls[i].p & config->masks->div_p_mask) << - config->masks->div_p_shift; - val &= ~(config->masks->div_n_mask << config->masks->div_n_shift); - val |= (tbls[i].n & config->masks->div_n_mask) << - config->masks->div_n_shift; - val &= ~(config->masks->dith_fdbk_m_mask << - config->masks->dith_fdbk_m_shift); - if (tbls[i].mode) - val |= (tbls[i].m & config->masks->dith_fdbk_m_mask) << - config->masks->dith_fdbk_m_shift; - else - val |= (tbls[i].m & config->masks->norm_fdbk_m_mask) << - config->masks->norm_fdbk_m_shift; - - writel(val, config->cfg_reg); - - clk->rate = rate; - - return 0; -} - -/* - * Calculates ahb, apb clk rate for specific value of div - */ -unsigned long bus_calc_rate(struct clk *clk, int index) -{ - unsigned long rate = clk->pclk->rate; - struct bus_rate_tbl *tbls = clk->rate_config.tbls; - - return rate / (tbls[index].div + 1); -} - -/* calculates current programmed rate of ahb or apb bus */ -int bus_clk_recalc(struct clk *clk) -{ - struct bus_clk_config *config = clk->private_data; - unsigned int div; - - div = ((readl(config->reg) >> config->masks->shift) & - config->masks->mask) + 1; - - if (!div) - return -EINVAL; - - clk->rate = (unsigned long)clk->pclk->rate / div; - return 0; -} - -/* Configures new clock rate of AHB OR APB bus */ -int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate) -{ - struct bus_rate_tbl *tbls = clk->rate_config.tbls; - struct bus_clk_config *config = clk->private_data; - unsigned long val, rate; - int i; - - i = round_rate_index(clk, desired_rate, &rate); - if (i < 0) - return i; - - val = readl(config->reg) & - ~(config->masks->mask << config->masks->shift); - val |= (tbls[i].div & config->masks->mask) << config->masks->shift; - writel(val, config->reg); - - clk->rate = rate; - - return 0; -} - -/* - * gives rate for different values of eq, x and y - * - * Fout from synthesizer can be given from two equations: - * Fout1 = (Fin * X/Y)/2 EQ1 - * Fout2 = Fin * X/Y EQ2 - */ -unsigned long aux_calc_rate(struct clk *clk, int index) -{ - unsigned long rate = clk->pclk->rate; - struct aux_rate_tbl *tbls = clk->rate_config.tbls; - u8 eq = tbls[index].eq ? 1 : 2; - - return (((rate/10000) * tbls[index].xscale) / - (tbls[index].yscale * eq)) * 10000; -} - -/* - * calculates current programmed rate of auxiliary synthesizers - * used by: UART, FIRDA - * - * Fout from synthesizer can be given from two equations: - * Fout1 = (Fin * X/Y)/2 - * Fout2 = Fin * X/Y - * - * Selection of eqn 1 or 2 is programmed in register - */ -int aux_clk_recalc(struct clk *clk) -{ - struct aux_clk_config *config = clk->private_data; - unsigned int num = 1, den = 1, val, eqn; - - val = readl(config->synth_reg); - - eqn = (val >> config->masks->eq_sel_shift) & - config->masks->eq_sel_mask; - if (eqn == config->masks->eq1_mask) - den *= 2; - - /* calculate numerator */ - num = (val >> config->masks->xscale_sel_shift) & - config->masks->xscale_sel_mask; - - /* calculate denominator */ - den *= (val >> config->masks->yscale_sel_shift) & - config->masks->yscale_sel_mask; - - if (!den) - return -EINVAL; - - clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000; - return 0; -} - -/* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/ -int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate) -{ - struct aux_rate_tbl *tbls = clk->rate_config.tbls; - struct aux_clk_config *config = clk->private_data; - unsigned long val, rate; - int i; - - i = round_rate_index(clk, desired_rate, &rate); - if (i < 0) - return i; - - val = readl(config->synth_reg) & - ~(config->masks->eq_sel_mask << config->masks->eq_sel_shift); - val |= (tbls[i].eq & config->masks->eq_sel_mask) << - config->masks->eq_sel_shift; - val &= ~(config->masks->xscale_sel_mask << - config->masks->xscale_sel_shift); - val |= (tbls[i].xscale & config->masks->xscale_sel_mask) << - config->masks->xscale_sel_shift; - val &= ~(config->masks->yscale_sel_mask << - config->masks->yscale_sel_shift); - val |= (tbls[i].yscale & config->masks->yscale_sel_mask) << - config->masks->yscale_sel_shift; - writel(val, config->synth_reg); - - clk->rate = rate; - - return 0; -} - -/* - * Calculates gpt clk rate for different values of mscale and nscale - * - * Fout= Fin/((2 ^ (N+1)) * (M+1)) - */ -unsigned long gpt_calc_rate(struct clk *clk, int index) -{ - unsigned long rate = clk->pclk->rate; - struct gpt_rate_tbl *tbls = clk->rate_config.tbls; - - return rate / ((1 << (tbls[index].nscale + 1)) * - (tbls[index].mscale + 1)); -} - -/* - * calculates current programmed rate of gpt synthesizers - * Fout from synthesizer can be given from below equations: - * Fout= Fin/((2 ^ (N+1)) * (M+1)) - */ -int gpt_clk_recalc(struct clk *clk) -{ - struct gpt_clk_config *config = clk->private_data; - unsigned int div = 1, val; - - val = readl(config->synth_reg); - div += (val >> config->masks->mscale_sel_shift) & - config->masks->mscale_sel_mask; - div *= 1 << (((val >> config->masks->nscale_sel_shift) & - config->masks->nscale_sel_mask) + 1); - - if (!div) - return -EINVAL; - - clk->rate = (unsigned long)clk->pclk->rate / div; - return 0; -} - -/* Configures new clock rate of gptiliary synthesizers used by: UART, FIRDA*/ -int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate) -{ - struct gpt_rate_tbl *tbls = clk->rate_config.tbls; - struct gpt_clk_config *config = clk->private_data; - unsigned long val, rate; - int i; - - i = round_rate_index(clk, desired_rate, &rate); - if (i < 0) - return i; - - val = readl(config->synth_reg) & ~(config->masks->mscale_sel_mask << - config->masks->mscale_sel_shift); - val |= (tbls[i].mscale & config->masks->mscale_sel_mask) << - config->masks->mscale_sel_shift; - val &= ~(config->masks->nscale_sel_mask << - config->masks->nscale_sel_shift); - val |= (tbls[i].nscale & config->masks->nscale_sel_mask) << - config->masks->nscale_sel_shift; - writel(val, config->synth_reg); - - clk->rate = rate; - - return 0; -} - -/* - * Calculates clcd clk rate for different values of div - * - * Fout from synthesizer can be given from below equation: - * Fout= Fin/2*div (division factor) - * div is 17 bits:- - * 0-13 (fractional part) - * 14-16 (integer part) - * To calculate Fout we left shift val by 14 bits and divide Fin by - * complete div (including fractional part) and then right shift the - * result by 14 places. - */ -unsigned long clcd_calc_rate(struct clk *clk, int index) -{ - unsigned long rate = clk->pclk->rate; - struct clcd_rate_tbl *tbls = clk->rate_config.tbls; - - rate /= 1000; - rate <<= 12; - rate /= (2 * tbls[index].div); - rate >>= 12; - rate *= 1000; - - return rate; -} - -/* - * calculates current programmed rate of clcd synthesizer - * Fout from synthesizer can be given from below equation: - * Fout= Fin/2*div (division factor) - * div is 17 bits:- - * 0-13 (fractional part) - * 14-16 (integer part) - * To calculate Fout we left shift val by 14 bits and divide Fin by - * complete div (including fractional part) and then right shift the - * result by 14 places. - */ -int clcd_clk_recalc(struct clk *clk) -{ - struct clcd_clk_config *config = clk->private_data; - unsigned int div = 1; - unsigned long prate; - unsigned int val; - - val = readl(config->synth_reg); - div = (val >> config->masks->div_factor_shift) & - config->masks->div_factor_mask; - - if (!div) - return -EINVAL; - - prate = clk->pclk->rate / 1000; /* first level division, make it KHz */ - - clk->rate = (((unsigned long)prate << 12) / (2 * div)) >> 12; - clk->rate *= 1000; - return 0; -} - -/* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/ -int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate) -{ - struct clcd_rate_tbl *tbls = clk->rate_config.tbls; - struct clcd_clk_config *config = clk->private_data; - unsigned long val, rate; - int i; - - i = round_rate_index(clk, desired_rate, &rate); - if (i < 0) - return i; - - val = readl(config->synth_reg) & ~(config->masks->div_factor_mask << - config->masks->div_factor_shift); - val |= (tbls[i].div & config->masks->div_factor_mask) << - config->masks->div_factor_shift; - writel(val, config->synth_reg); - - clk->rate = rate; - - return 0; -} - -/* - * Used for clocks that always have value as the parent clock divided by a - * fixed divisor - */ -int follow_parent(struct clk *clk) -{ - unsigned int div_factor = (clk->div_factor < 1) ? 1 : clk->div_factor; - - clk->rate = clk->pclk->rate/div_factor; - return 0; -} - -/** - * recalc_root_clocks - recalculate and propagate all root clocks - * - * Recalculates all root clocks (clocks with no parent), which if the - * clock's .recalc is set correctly, should also propagate their rates. - */ -void recalc_root_clocks(void) -{ - struct clk *pclk; - unsigned long flags; - int ret = 0; - - spin_lock_irqsave(&clocks_lock, flags); - list_for_each_entry(pclk, &root_clks, sibling) { - if (pclk->recalc) { - ret = pclk->recalc(pclk); - /* - * recalc will return error if clk out is not programmed - * In this case configure default clock. - */ - if (ret && pclk->set_rate) - pclk->set_rate(pclk, 0); - } - propagate_rate(pclk, 1); - /* Enable clks enabled on init, in software view */ - if (pclk->flags & ENABLED_ON_INIT) - do_clk_enable(pclk); - } - spin_unlock_irqrestore(&clocks_lock, flags); -} - -void __init clk_init(void) -{ - recalc_root_clocks(); -} - -#ifdef CONFIG_DEBUG_FS -/* - * debugfs support to trace clock tree hierarchy and attributes - */ -static struct dentry *clk_debugfs_root; -static int clk_debugfs_register_one(struct clk *c) -{ - int err; - struct dentry *d; - struct clk *pa = c->pclk; - char s[255]; - char *p = s; - - if (c) { - if (c->cl->con_id) - p += sprintf(p, "%s", c->cl->con_id); - if (c->cl->dev_id) - p += sprintf(p, "%s", c->cl->dev_id); - } - d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root); - if (!d) - return -ENOMEM; - c->dent = d; - - d = debugfs_create_u32("usage_count", S_IRUGO, c->dent, - (u32 *)&c->usage_count); - if (!d) { - err = -ENOMEM; - goto err_out; - } - d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate); - if (!d) { - err = -ENOMEM; - goto err_out; - } - d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags); - if (!d) { - err = -ENOMEM; - goto err_out; - } - return 0; - -err_out: - debugfs_remove_recursive(c->dent); - return err; -} - -static int clk_debugfs_register(struct clk *c) -{ - int err; - struct clk *pa = c->pclk; - - if (pa && !pa->dent) { - err = clk_debugfs_register(pa); - if (err) - return err; - } - - if (!c->dent) { - err = clk_debugfs_register_one(c); - if (err) - return err; - } - return 0; -} - -static int __init clk_debugfs_init(void) -{ - struct clk *c; - struct dentry *d; - int err; - - d = debugfs_create_dir("clock", NULL); - if (!d) - return -ENOMEM; - clk_debugfs_root = d; - - list_for_each_entry(c, &clocks, node) { - err = clk_debugfs_register(c); - if (err) - goto err_out; - } - return 0; -err_out: - debugfs_remove_recursive(clk_debugfs_root); - return err; -} -late_initcall(clk_debugfs_init); - -static int clk_debugfs_reparent(struct clk *c) -{ - debugfs_remove(c->dent); - return clk_debugfs_register_one(c); -} -#endif /* CONFIG_DEBUG_FS */ diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h deleted file mode 100644 index 0062bafef12d..000000000000 --- a/arch/arm/plat-spear/include/plat/clock.h +++ /dev/null @@ -1,249 +0,0 @@ -/* - * arch/arm/plat-spear/include/plat/clock.h - * - * Clock framework definitions for SPEAr platform - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __PLAT_CLOCK_H -#define __PLAT_CLOCK_H - -#include <linux/list.h> -#include <linux/clkdev.h> -#include <linux/types.h> - -/* clk structure flags */ -#define ALWAYS_ENABLED (1 << 0) /* clock always enabled */ -#define RESET_TO_ENABLE (1 << 1) /* reset register bit to enable clk */ -#define ENABLED_ON_INIT (1 << 2) /* clocks enabled at init */ - -/** - * struct clkops - clock operations - * @enable: pointer to clock enable function - * @disable: pointer to clock disable function - */ -struct clkops { - int (*enable) (struct clk *); - void (*disable) (struct clk *); -}; - -/** - * struct pclk_info - parents info - * @pclk: pointer to parent clk - * @pclk_val: value to be written for selecting this parent - */ -struct pclk_info { - struct clk *pclk; - u8 pclk_val; -}; - -/** - * struct pclk_sel - parents selection configuration - * @pclk_info: pointer to array of parent clock info - * @pclk_count: number of parents - * @pclk_sel_reg: register for selecting a parent - * @pclk_sel_mask: mask for selecting parent (can be used to clear bits also) - */ -struct pclk_sel { - struct pclk_info *pclk_info; - u8 pclk_count; - void __iomem *pclk_sel_reg; - unsigned int pclk_sel_mask; -}; - -/** - * struct rate_config - clk rate configurations - * @tbls: array of device specific clk rate tables, in ascending order of rates - * @count: size of tbls array - * @default_index: default setting when originally disabled - */ -struct rate_config { - void *tbls; - u8 count; - u8 default_index; -}; - -/** - * struct clk - clock structure - * @usage_count: num of users who enabled this clock - * @flags: flags for clock properties - * @rate: programmed clock rate in Hz - * @en_reg: clk enable/disable reg - * @en_reg_bit: clk enable/disable bit - * @ops: clk enable/disable ops - generic_clkops selected if NULL - * @recalc: pointer to clock rate recalculate function - * @set_rate: pointer to clock set rate function - * @calc_rate: pointer to clock get rate function for index - * @rate_config: rate configuration information, used by set_rate - * @div_factor: division factor to parent clock. - * @pclk: current parent clk - * @pclk_sel: pointer to parent selection structure - * @pclk_sel_shift: register shift for selecting parent of this clock - * @children: list for childrens or this clock - * @sibling: node for list of clocks having same parents - * @private_data: clock specific private data - * @node: list to maintain clocks linearly - * @cl: clocklook up associated with this clock - * @dent: object for debugfs - */ -struct clk { - unsigned int usage_count; - unsigned int flags; - unsigned long rate; - void __iomem *en_reg; - u8 en_reg_bit; - const struct clkops *ops; - int (*recalc) (struct clk *); - int (*set_rate) (struct clk *, unsigned long rate); - unsigned long (*calc_rate)(struct clk *, int index); - struct rate_config rate_config; - unsigned int div_factor; - - struct clk *pclk; - struct pclk_sel *pclk_sel; - unsigned int pclk_sel_shift; - - struct list_head children; - struct list_head sibling; - void *private_data; -#ifdef CONFIG_DEBUG_FS - struct list_head node; - struct clk_lookup *cl; - struct dentry *dent; -#endif -}; - -/* pll configuration structure */ -struct pll_clk_masks { - u32 mode_mask; - u32 mode_shift; - - u32 norm_fdbk_m_mask; - u32 norm_fdbk_m_shift; - u32 dith_fdbk_m_mask; - u32 dith_fdbk_m_shift; - u32 div_p_mask; - u32 div_p_shift; - u32 div_n_mask; - u32 div_n_shift; -}; - -struct pll_clk_config { - void __iomem *mode_reg; - void __iomem *cfg_reg; - struct pll_clk_masks *masks; -}; - -/* pll clk rate config structure */ -struct pll_rate_tbl { - u8 mode; - u16 m; - u8 n; - u8 p; -}; - -/* ahb and apb bus configuration structure */ -struct bus_clk_masks { - u32 mask; - u32 shift; -}; - -struct bus_clk_config { - void __iomem *reg; - struct bus_clk_masks *masks; -}; - -/* ahb and apb clk bus rate config structure */ -struct bus_rate_tbl { - u8 div; -}; - -/* Aux clk configuration structure: applicable to UART and FIRDA */ -struct aux_clk_masks { - u32 eq_sel_mask; - u32 eq_sel_shift; - u32 eq1_mask; - u32 eq2_mask; - u32 xscale_sel_mask; - u32 xscale_sel_shift; - u32 yscale_sel_mask; - u32 yscale_sel_shift; -}; - -struct aux_clk_config { - void __iomem *synth_reg; - struct aux_clk_masks *masks; -}; - -/* aux clk rate config structure */ -struct aux_rate_tbl { - u16 xscale; - u16 yscale; - u8 eq; -}; - -/* GPT clk configuration structure */ -struct gpt_clk_masks { - u32 mscale_sel_mask; - u32 mscale_sel_shift; - u32 nscale_sel_mask; - u32 nscale_sel_shift; -}; - -struct gpt_clk_config { - void __iomem *synth_reg; - struct gpt_clk_masks *masks; -}; - -/* gpt clk rate config structure */ -struct gpt_rate_tbl { - u16 mscale; - u16 nscale; -}; - -/* clcd clk configuration structure */ -struct clcd_synth_masks { - u32 div_factor_mask; - u32 div_factor_shift; -}; - -struct clcd_clk_config { - void __iomem *synth_reg; - struct clcd_synth_masks *masks; -}; - -/* clcd clk rate config structure */ -struct clcd_rate_tbl { - u16 div; -}; - -/* platform specific clock functions */ -void __init clk_init(void); -void clk_register(struct clk_lookup *cl); -void recalc_root_clocks(void); - -/* clock recalc & set rate functions */ -int follow_parent(struct clk *clk); -unsigned long pll_calc_rate(struct clk *clk, int index); -int pll_clk_recalc(struct clk *clk); -int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate); -unsigned long bus_calc_rate(struct clk *clk, int index); -int bus_clk_recalc(struct clk *clk); -int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate); -unsigned long gpt_calc_rate(struct clk *clk, int index); -int gpt_clk_recalc(struct clk *clk); -int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate); -unsigned long aux_calc_rate(struct clk *clk, int index); -int aux_clk_recalc(struct clk *clk); -int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate); -unsigned long clcd_calc_rate(struct clk *clk, int index); -int clcd_clk_recalc(struct clk *clk); -int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate); - -#endif /* __PLAT_CLOCK_H */ diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/plat-spear/include/plat/debug-macro.S index 02b160a1ec9b..ab3de721c5db 100644 --- a/arch/arm/plat-spear/include/plat/debug-macro.S +++ b/arch/arm/plat-spear/include/plat/debug-macro.S @@ -12,7 +12,7 @@ */ #include <linux/amba/serial.h> -#include <mach/hardware.h> +#include <mach/spear.h> .macro addruart, rp, rv, tmp mov \rp, #SPEAR_DBG_UART_BASE @ Physical base diff --git a/arch/arm/plat-spear/include/plat/hardware.h b/arch/arm/plat-spear/include/plat/hardware.h deleted file mode 100644 index 70187d763e26..000000000000 --- a/arch/arm/plat-spear/include/plat/hardware.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * arch/arm/plat-spear/include/plat/hardware.h - * - * Hardware definitions for SPEAr - * - * Copyright (C) 2010 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __PLAT_HARDWARE_H -#define __PLAT_HARDWARE_H - -#endif /* __PLAT_HARDWARE_H */ diff --git a/arch/arm/plat-spear/include/plat/padmux.h b/arch/arm/plat-spear/include/plat/padmux.h deleted file mode 100644 index 877f3adcf610..000000000000 --- a/arch/arm/plat-spear/include/plat/padmux.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * arch/arm/plat-spear/include/plat/padmux.h - * - * SPEAr platform specific gpio pads muxing file - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __PLAT_PADMUX_H -#define __PLAT_PADMUX_H - -#include <linux/types.h> - -/* - * struct pmx_reg: configuration structure for mode reg and mux reg - * - * offset: offset of mode reg - * mask: mask of mode reg - */ -struct pmx_reg { - u32 offset; - u32 mask; -}; - -/* - * struct pmx_dev_mode: configuration structure every group of modes of a device - * - * ids: all modes for this configuration - * mask: mask for supported mode - */ -struct pmx_dev_mode { - u32 ids; - u32 mask; -}; - -/* - * struct pmx_mode: mode definition structure - * - * name: mode name - * mask: mode mask - */ -struct pmx_mode { - char *name; - u32 id; - u32 mask; -}; - -/* - * struct pmx_dev: device definition structure - * - * name: device name - * modes: device configuration array for different modes supported - * mode_count: size of modes array - * is_active: is peripheral active/enabled - * enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg - */ -struct pmx_dev { - char *name; - struct pmx_dev_mode *modes; - u8 mode_count; - bool is_active; - bool enb_on_reset; -}; - -/* - * struct pmx_driver: driver definition structure - * - * mode: mode to be set - * devs: array of pointer to pmx devices - * devs_count: ARRAY_SIZE of devs - * base: base address of soc config registers - * mode_reg: structure of mode config register - * mux_reg: structure of device mux config register - */ -struct pmx_driver { - struct pmx_mode *mode; - struct pmx_dev **devs; - u8 devs_count; - u32 *base; - struct pmx_reg mode_reg; - struct pmx_reg mux_reg; -}; - -/* pmx functions */ -int pmx_register(struct pmx_driver *driver); - -#endif /* __PLAT_PADMUX_H */ diff --git a/arch/arm/plat-spear/include/plat/pl080.h b/arch/arm/plat-spear/include/plat/pl080.h new file mode 100644 index 000000000000..e14a3e4932f9 --- /dev/null +++ b/arch/arm/plat-spear/include/plat/pl080.h @@ -0,0 +1,21 @@ +/* + * arch/arm/plat-spear/include/plat/pl080.h + * + * DMAC pl080 definitions for SPEAr platform + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_PL080_H +#define __PLAT_PL080_H + +struct pl08x_dma_chan; +int pl080_get_signal(struct pl08x_dma_chan *ch); +void pl080_put_signal(struct pl08x_dma_chan *ch); + +#endif /* __PLAT_PL080_H */ diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/plat-spear/include/plat/uncompress.h index 1bf84527aee4..6dd455bafdfd 100644 --- a/arch/arm/plat-spear/include/plat/uncompress.h +++ b/arch/arm/plat-spear/include/plat/uncompress.h @@ -13,7 +13,7 @@ #include <linux/io.h> #include <linux/amba/serial.h> -#include <mach/hardware.h> +#include <mach/spear.h> #ifndef __PLAT_UNCOMPRESS_H #define __PLAT_UNCOMPRESS_H diff --git a/arch/arm/plat-spear/padmux.c b/arch/arm/plat-spear/padmux.c deleted file mode 100644 index 555eec6dc1cb..000000000000 --- a/arch/arm/plat-spear/padmux.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * arch/arm/plat-spear/include/plat/padmux.c - * - * SPEAr platform specific gpio pads muxing source file - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar<viresh.kumar@st.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/err.h> -#include <linux/io.h> -#include <linux/slab.h> -#include <plat/padmux.h> - -/* - * struct pmx: pmx definition structure - * - * base: base address of configuration registers - * mode_reg: mode configurations - * mux_reg: muxing configurations - * active_mode: pointer to current active mode - */ -struct pmx { - u32 base; - struct pmx_reg mode_reg; - struct pmx_reg mux_reg; - struct pmx_mode *active_mode; -}; - -static struct pmx *pmx; - -/** - * pmx_mode_set - Enables an multiplexing mode - * @mode - pointer to pmx mode - * - * It will set mode of operation in hardware. - * Returns -ve on Err otherwise 0 - */ -static int pmx_mode_set(struct pmx_mode *mode) -{ - u32 val; - - if (!mode->name) - return -EFAULT; - - pmx->active_mode = mode; - - val = readl(pmx->base + pmx->mode_reg.offset); - val &= ~pmx->mode_reg.mask; - val |= mode->mask & pmx->mode_reg.mask; - writel(val, pmx->base + pmx->mode_reg.offset); - - return 0; -} - -/** - * pmx_devs_enable - Enables list of devices - * @devs - pointer to pmx device array - * @count - number of devices to enable - * - * It will enable pads for all required peripherals once and only once. - * If peripheral is not supported by current mode then request is rejected. - * Conflicts between peripherals are not handled and peripherals will be - * enabled in the order they are present in pmx_dev array. - * In case of conflicts last peripheral enabled will be present. - * Returns -ve on Err otherwise 0 - */ -static int pmx_devs_enable(struct pmx_dev **devs, u8 count) -{ - u32 val, i, mask; - - if (!count) - return -EINVAL; - - val = readl(pmx->base + pmx->mux_reg.offset); - for (i = 0; i < count; i++) { - u8 j = 0; - - if (!devs[i]->name || !devs[i]->modes) { - printk(KERN_ERR "padmux: dev name or modes is null\n"); - continue; - } - /* check if peripheral exists in active mode */ - if (pmx->active_mode) { - bool found = false; - for (j = 0; j < devs[i]->mode_count; j++) { - if (devs[i]->modes[j].ids & - pmx->active_mode->id) { - found = true; - break; - } - } - if (found == false) { - printk(KERN_ERR "%s device not available in %s"\ - "mode\n", devs[i]->name, - pmx->active_mode->name); - continue; - } - } - - /* enable peripheral */ - mask = devs[i]->modes[j].mask & pmx->mux_reg.mask; - if (devs[i]->enb_on_reset) - val &= ~mask; - else - val |= mask; - - devs[i]->is_active = true; - } - writel(val, pmx->base + pmx->mux_reg.offset); - kfree(pmx); - - /* this will ensure that multiplexing can't be changed now */ - pmx = (struct pmx *)-1; - - return 0; -} - -/** - * pmx_register - registers a platform requesting pad mux feature - * @driver - pointer to driver structure containing driver specific parameters - * - * Also this must be called only once. This will allocate memory for pmx - * structure, will call pmx_mode_set, will call pmx_devs_enable. - * Returns -ve on Err otherwise 0 - */ -int pmx_register(struct pmx_driver *driver) -{ - int ret = 0; - - if (pmx) - return -EPERM; - if (!driver->base || !driver->devs) - return -EFAULT; - - pmx = kzalloc(sizeof(*pmx), GFP_KERNEL); - if (!pmx) - return -ENOMEM; - - pmx->base = (u32)driver->base; - pmx->mode_reg.offset = driver->mode_reg.offset; - pmx->mode_reg.mask = driver->mode_reg.mask; - pmx->mux_reg.offset = driver->mux_reg.offset; - pmx->mux_reg.mask = driver->mux_reg.mask; - - /* choose mode to enable */ - if (driver->mode) { - ret = pmx_mode_set(driver->mode); - if (ret) - goto pmx_fail; - } - ret = pmx_devs_enable(driver->devs, driver->devs_count); - if (ret) - goto pmx_fail; - - return 0; - -pmx_fail: - return ret; -} diff --git a/arch/arm/plat-spear/pl080.c b/arch/arm/plat-spear/pl080.c new file mode 100644 index 000000000000..a56a067717c1 --- /dev/null +++ b/arch/arm/plat-spear/pl080.c @@ -0,0 +1,80 @@ +/* + * arch/arm/plat-spear/pl080.c + * + * DMAC pl080 definitions for SPEAr platform + * + * Copyright (C) 2012 ST Microelectronics + * Viresh Kumar <viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/amba/pl08x.h> +#include <linux/amba/bus.h> +#include <linux/bug.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/spinlock_types.h> +#include <mach/spear.h> +#include <mach/misc_regs.h> + +static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x); + +struct { + unsigned char busy; + unsigned char val; +} signals[16] = {{0, 0}, }; + +int pl080_get_signal(struct pl08x_dma_chan *ch) +{ + const struct pl08x_channel_data *cd = ch->cd; + unsigned int signal = cd->min_signal, val; + unsigned long flags; + + spin_lock_irqsave(&lock, flags); + + /* Return if signal is already acquired by somebody else */ + if (signals[signal].busy && + (signals[signal].val != cd->muxval)) { + spin_unlock_irqrestore(&lock, flags); + return -EBUSY; + } + + /* If acquiring for the first time, configure it */ + if (!signals[signal].busy) { + val = readl(DMA_CHN_CFG); + + /* + * Each request line has two bits in DMA_CHN_CFG register. To + * goto the bits of current request line, do left shift of + * value by 2 * signal number. + */ + val &= ~(0x3 << (signal * 2)); + val |= cd->muxval << (signal * 2); + writel(val, DMA_CHN_CFG); + } + + signals[signal].busy++; + signals[signal].val = cd->muxval; + spin_unlock_irqrestore(&lock, flags); + + return signal; +} + +void pl080_put_signal(struct pl08x_dma_chan *ch) +{ + const struct pl08x_channel_data *cd = ch->cd; + unsigned long flags; + + spin_lock_irqsave(&lock, flags); + + /* if signal is not used */ + if (!signals[cd->min_signal].busy) + BUG(); + + signals[cd->min_signal].busy--; + + spin_unlock_irqrestore(&lock, flags); +} diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/plat-spear/restart.c index 16f203e78d89..ea0a61302b7e 100644 --- a/arch/arm/plat-spear/restart.c +++ b/arch/arm/plat-spear/restart.c @@ -13,9 +13,10 @@ #include <linux/io.h> #include <asm/system_misc.h> #include <asm/hardware/sp810.h> -#include <mach/hardware.h> +#include <mach/spear.h> #include <mach/generic.h> +#define SPEAR13XX_SYS_SW_RES (VA_MISC_BASE + 0x204) void spear_restart(char mode, const char *cmd) { if (mode == 's') { @@ -23,6 +24,10 @@ void spear_restart(char mode, const char *cmd) soft_restart(0); } else { /* hardware reset, Use on-chip reset capability */ +#ifdef CONFIG_ARCH_SPEAR13XX + writel_relaxed(0x01, SPEAR13XX_SYS_SW_RES); +#else sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE); +#endif } } diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c index abb5bdecd509..03321af5de9f 100644 --- a/arch/arm/plat-spear/time.c +++ b/arch/arm/plat-spear/time.c @@ -15,14 +15,15 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/interrupt.h> +#include <linux/ioport.h> #include <linux/io.h> #include <linux/kernel.h> +#include <linux/of_irq.h> +#include <linux/of_address.h> #include <linux/time.h> #include <linux/irq.h> #include <asm/mach/time.h> #include <mach/generic.h> -#include <mach/hardware.h> -#include <mach/irqs.h> /* * We would use TIMER0 and TIMER1 as clockevent and clocksource. @@ -175,7 +176,7 @@ static struct irqaction spear_timer_irq = { .handler = spear_timer_interrupt }; -static void __init spear_clockevent_init(void) +static void __init spear_clockevent_init(int irq) { u32 tick_rate; @@ -195,22 +196,35 @@ static void __init spear_clockevent_init(void) clockevents_register_device(&clkevt); - setup_irq(SPEAR_GPT0_CHAN0_IRQ, &spear_timer_irq); + setup_irq(irq, &spear_timer_irq); } -void __init spear_setup_timer(void) +const static struct of_device_id timer_of_match[] __initconst = { + { .compatible = "st,spear-timer", }, + { }, +}; + +void __init spear_setup_of_timer(void) { - int ret; + struct device_node *np; + int irq, ret; + + np = of_find_matching_node(NULL, timer_of_match); + if (!np) { + pr_err("%s: No timer passed via DT\n", __func__); + return; + } - if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) { - pr_err("%s:cannot get IO addr\n", __func__); + irq = irq_of_parse_and_map(np, 0); + if (!irq) { + pr_err("%s: No irq passed for timer via DT\n", __func__); return; } - gpt_base = (void __iomem *)ioremap(SPEAR_GPT0_BASE, SZ_1K); + gpt_base = of_iomap(np, 0); if (!gpt_base) { - pr_err("%s:ioremap failed for gpt\n", __func__); - goto err_mem; + pr_err("%s: of iomap failed\n", __func__); + return; } gpt_clk = clk_get_sys("gpt0", NULL); @@ -219,21 +233,19 @@ void __init spear_setup_timer(void) goto err_iomap; } - ret = clk_enable(gpt_clk); + ret = clk_prepare_enable(gpt_clk); if (ret < 0) { - pr_err("%s:couldn't enable gpt clock\n", __func__); - goto err_clk; + pr_err("%s:couldn't prepare-enable gpt clock\n", __func__); + goto err_prepare_enable_clk; } - spear_clockevent_init(); + spear_clockevent_init(irq); spear_clocksource_init(); return; -err_clk: +err_prepare_enable_clk: clk_put(gpt_clk); err_iomap: iounmap(gpt_base); -err_mem: - release_mem_region(SPEAR_GPT0_BASE, SZ_1K); } |