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author | Richard Kuo <rkuo@codeaurora.org> | 2014-04-15 22:41:17 +0200 |
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committer | Richard Kuo <rkuo@codeaurora.org> | 2014-12-16 20:27:30 +0100 |
commit | ea0f1b92150fb368d26e38c0a0e9ab244b95be03 (patch) | |
tree | c1d86aa546b3165bcdd0a1f4607e04587f7bbda7 /arch | |
parent | Hexagon: fix alignment of init_task in RW_DATA_SECTION (diff) | |
download | linux-ea0f1b92150fb368d26e38c0a0e9ab244b95be03.tar.xz linux-ea0f1b92150fb368d26e38c0a0e9ab244b95be03.zip |
Hexagon: set ARCH_DMA_MINALIGN
Signed-off-by: Richard Kuo <rkuo@codeaurora.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/hexagon/include/asm/cache.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/hexagon/include/asm/cache.h b/arch/hexagon/include/asm/cache.h index 263511719a4a..69952c184207 100644 --- a/arch/hexagon/include/asm/cache.h +++ b/arch/hexagon/include/asm/cache.h @@ -1,7 +1,7 @@ /* * Cache definitions for the Hexagon architecture * - * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved. + * Copyright (c) 2010-2011,2014 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -25,6 +25,8 @@ #define L1_CACHE_SHIFT (5) #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES + #define __cacheline_aligned __aligned(L1_CACHE_BYTES) #define ____cacheline_aligned __aligned(L1_CACHE_BYTES) |