diff options
author | Ben Dooks <ben-linux@fluff.org> | 2008-04-16 01:15:20 +0200 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-04-17 18:04:41 +0200 |
commit | 3c7d9c81e1302c244180e62999a08ca95b175cf5 (patch) | |
tree | a67961f6c0435e0a1965df9770433c73cdfe1664 /arch | |
parent | [ARM] 4986/1: S3C24XX: Simtec machines need UCLK as parent to DCLK (diff) | |
download | linux-3c7d9c81e1302c244180e62999a08ca95b175cf5.tar.xz linux-3c7d9c81e1302c244180e62999a08ca95b175cf5.zip |
[ARM] 4987/1: S3C24XX: Ensure watchdog reset initiated from cached code.
There seems to be some problem with at-least the S3C2440 and
bus traffic during an reset. It is unlikely, but still possible
that the system will hang in such a way that the watchdog cannot
get the system out of the state it is in.
Change to making the code that calls the watchdog reset run from
cached memory so that instruction fetches have quiesced before the
watchdog fires.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/plat-s3c24xx/cpu.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c index f513ab083b8f..f5699cadb0c3 100644 --- a/arch/arm/plat-s3c24xx/cpu.c +++ b/arch/arm/plat-s3c24xx/cpu.c @@ -28,15 +28,19 @@ #include <linux/ioport.h> #include <linux/serial_core.h> #include <linux/platform_device.h> +#include <linux/delay.h> #include <asm/hardware.h> #include <asm/irq.h> #include <asm/io.h> #include <asm/delay.h> +#include <asm/cacheflush.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> +#include <asm/arch/system-reset.h> + #include <asm/arch/regs-gpio.h> #include <asm/plat-s3c/regs-serial.h> @@ -203,6 +207,27 @@ static unsigned long s3c24xx_read_idcode_v4(void) #endif } +/* Hook for arm_pm_restart to ensure we execute the reset code + * with the caches enabled. It seems at least the S3C2440 has a problem + * resetting if there is bus activity interrupted by the reset. + */ +static void s3c24xx_pm_restart(char mode) +{ + if (mode != 's') { + unsigned long flags; + + local_irq_save(flags); + __cpuc_flush_kern_all(); + __cpuc_flush_user_all(); + + arch_reset(mode); + local_irq_restore(flags); + } + + /* fallback, or unhandled */ + arm_machine_restart(mode); +} + void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) { unsigned long idcode = 0x0; @@ -230,6 +255,8 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) panic("Unsupported S3C24XX CPU"); } + arm_pm_restart = s3c24xx_pm_restart; + (cpu->map_io)(mach_desc, size); } |