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authorRalf Baechle <ralf@linux-mips.org>2012-10-17 00:39:09 +0200
committerRalf Baechle <ralf@linux-mips.org>2012-12-12 16:48:49 +0100
commitf65aad41772f6a0022e9763fe06f47604449964c (patch)
tree701d6ea74ac0c41f008c5554d876945fe4caf512 /arch
parentMIPS: Control huge tlb support via Kconfig symbol MIPS_HUGE_TLB_SUPPORT (diff)
downloadlinux-f65aad41772f6a0022e9763fe06f47604449964c.tar.xz
linux-f65aad41772f6a0022e9763fe06f47604449964c.zip
MIPS: Cavium: Add EDAC support.
Drivers for EDAC on Cavium. Supported subsystems are: o CPU primary caches. These are parity protected only, so only error reporting. o Second level cache - ECC protected, provides SECDED. o Memory: ECC / SECDEC if used with suitable DRAM modules. The driver will will only initialize if ECC is enabled on a system so is safe to run on non-ECC memory. o PCI: Parity error reporting Since it is very hard to test this sort of code the implementation is very conservative and uses polling where possible for now. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Reviewed-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/Kconfig1
-rw-r--r--arch/mips/cavium-octeon/setup.c30
-rw-r--r--arch/mips/mm/c-octeon.c46
-rw-r--r--arch/mips/pci/pci-octeon.c4
4 files changed, 58 insertions, 23 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 397194a263ce..b47d591c03dd 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -774,6 +774,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
select DMA_COHERENT
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
+ select EDAC_SUPPORT
select SYS_SUPPORTS_HOTPLUG_CPU
select SYS_HAS_EARLY_PRINTK
select SYS_HAS_CPU_CAVIUM_OCTEON
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 04dd8ff0e0d8..60ed700a956d 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -4,9 +4,11 @@
* for more details.
*
* Copyright (C) 2004-2007 Cavium Networks
- * Copyright (C) 2008 Wind River Systems
+ * Copyright (C) 2008, 2009 Wind River Systems
+ * written by Ralf Baechle <ralf@linux-mips.org>
*/
#include <linux/init.h>
+#include <linux/kernel.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/export.h>
@@ -821,3 +823,29 @@ void __init device_tree_init(void)
}
unflatten_device_tree();
}
+
+static char *edac_device_names[] = {
+ "co_l2c_edac",
+ "co_lmc_edac",
+ "co_pc_edac",
+};
+
+static int __init edac_devinit(void)
+{
+ struct platform_device *dev;
+ int i, err = 0;
+ char *name;
+
+ for (i = 0; i < ARRAY_SIZE(edac_device_names); i++) {
+ name = edac_device_names[i];
+ dev = platform_device_register_simple(name, -1, NULL, 0);
+ if (IS_ERR(dev)) {
+ pr_err("Registation of %s failed!\n", name);
+ err = PTR_ERR(dev);
+ }
+ }
+
+ return err;
+}
+
+device_initcall(edac_devinit);
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index 44e69e7a4519..9f67553762d5 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -5,6 +5,7 @@
*
* Copyright (C) 2005-2007 Cavium Networks
*/
+#include <linux/export.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
@@ -28,6 +29,7 @@
#include <asm/octeon/octeon.h>
unsigned long long cache_err_dcache[NR_CPUS];
+EXPORT_SYMBOL_GPL(cache_err_dcache);
/**
* Octeon automatically flushes the dcache on tlb changes, so
@@ -288,42 +290,42 @@ void __cpuinit octeon_cache_init(void)
* Handle a cache error exception
*/
-static void cache_parity_error_octeon(int non_recoverable)
+static RAW_NOTIFIER_HEAD(co_cache_error_chain);
+
+int register_co_cache_error_notifier(struct notifier_block *nb)
{
- unsigned long coreid = cvmx_get_core_num();
- uint64_t icache_err = read_octeon_c0_icacheerr();
-
- pr_err("Cache error exception:\n");
- pr_err("cp0_errorepc == %lx\n", read_c0_errorepc());
- if (icache_err & 1) {
- pr_err("CacheErr (Icache) == %llx\n",
- (unsigned long long)icache_err);
- write_octeon_c0_icacheerr(0);
- }
- if (cache_err_dcache[coreid] & 1) {
- pr_err("CacheErr (Dcache) == %llx\n",
- (unsigned long long)cache_err_dcache[coreid]);
- cache_err_dcache[coreid] = 0;
- }
+ return raw_notifier_chain_register(&co_cache_error_chain, nb);
+}
+EXPORT_SYMBOL_GPL(register_co_cache_error_notifier);
- if (non_recoverable)
- panic("Can't handle cache error: nested exception");
+int unregister_co_cache_error_notifier(struct notifier_block *nb)
+{
+ return raw_notifier_chain_unregister(&co_cache_error_chain, nb);
+}
+EXPORT_SYMBOL_GPL(unregister_co_cache_error_notifier);
+
+static inline int co_cache_error_call_notifiers(unsigned long val)
+{
+ return raw_notifier_call_chain(&co_cache_error_chain, val, NULL);
}
/**
* Called when the the exception is recoverable
*/
-
asmlinkage void cache_parity_error_octeon_recoverable(void)
{
- cache_parity_error_octeon(0);
+ co_cache_error_call_notifiers(0);
}
/**
* Called when the the exception is not recoverable
+ *
+ * The issue not that the cache error exception itself was non-recoverable
+ * but that due to nesting of exception may have lost some state so can't
+ * continue.
*/
-
asmlinkage void cache_parity_error_octeon_non_recoverable(void)
{
- cache_parity_error_octeon(1);
+ co_cache_error_call_notifiers(1);
+ panic("Can't handle cache error: nested exception");
}
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index 4b0c347d7a82..8eb2ee345d03 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -11,6 +11,7 @@
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/delay.h>
+#include <linux/platform_device.h>
#include <linux/swiotlb.h>
#include <asm/time.h>
@@ -704,6 +705,9 @@ static int __init octeon_pci_setup(void)
*/
cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);
+ if (IS_ERR(platform_device_register_simple("co_pci_edac", 0, NULL, 0)))
+ pr_err("Registation of co_pci_edac failed!\n");
+
octeon_pci_dma_init();
return 0;